This PDF file contains the front matter associated with SPIE Proceedings Volume 12053, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

In case the process margin of the device is large and the defect tendency in the wafer occurs randomly, process monitoring were possible using limited sampling measurement values. Previous 3D structure metrology equipment (CD-SEM, ellipsometry, etc.) are not able to measure the entire structure of the wafer due to the speed limit. If the measurement location does not include a weak point, an error occurs in predicting the wafer defect rate. In this study, we propose a new method that can extract weak points from color maps obtained by high-speed inspection tools that can measure the entire wafer. We were able to reduce the process error by about 20% by weak point monitoring.

The flatness of the silicon wafers used to manufacture integrated circuits (IC) is controlled to tight tolerances to help ensure that the full wafer is sufficiently flat for lithographic processing1. Chemical-Mechanical Planarization (CMP) is one of many processes outside the lithographic sector that will influence wafer flatness across each image lithographic exposure section field and across the wafer2. Advanced lithographic patterning processes require a detailed map of the wafer shape to avoid overlay errors caused by depth-of-focus issues1. In recent years, a metrology tool named PWG5TM (Patterned Wafer Geometry, 5th generation), based on using double Fizeau interferometry to generate phase changes from the interferometric pattern applied to the reflective surface, has been used to generate a wafer geometry map to correct for process induced focus issues as well as overlay problems2. In this paper we present Wave Front Phase Imaging (WFPI); a new patterned wafer geometry technique that measures the wave front phase utilizing two intensity images of the light reflected off the patterned wafer. We show that the 300mm machine acquires 7.65 million data points in 5 seconds on the full 300mm patterned wafer with a lateral resolution of 96μm.

The semiconductor industry needs to fit ever more devices per unit area to improve their performance; hence a trend towards increasingly complex structures by varying material combinations and 3D geometries with increasing aspect ratios. The new materials used may be optically opaque, posing problems for traditional optical metrology methods. One solution is to use acoustical waves, which present the double advantage of not being hampered by optically opaque layers and allowing for penetration depths of 10’s of μm at sub-μm wavelengths; which is considerably larger than most traditional optical methods (O(100 nm’s - μm’s)). Here, we present a novel acoustic metrology method using GHz ultrasound waves to measure deeply buried subsurface features (<5 μm). The concept consisted of a GHz acoustic transducer integrated above the tip of a custom designed probe, which is then scanned across a sample. The method uses non-damaging solid-solid contact without the need for liquid coupling layers – in contrast to conventional acoustical microscopy. This allows for the use of much higher acoustic frequencies, hence higher on-axis resolutions. The transducer is used in pulse-echo mode and a stage controller is used to move the probe for scanning. An experimental setup was built with a 4 GHz transducer and tested successfully on 1.5-2 μm size features buried below a 5 μm PMMA or 10 μm SiO2 layer, respectively. A good match was further obtained between the measurements and the model predictions. These results demonstrated the feasibility of the new method, opening new opportunities for metrology and inspection applications.

We report on enhanced detection of strain waves in gold gratings, using a probe laser pulse tuned at and close to the surface plasmon-polariton (SPP) resonance of the gratings. The enhancement, of up to twenty times, is observed in the strain-wave-induced reaction changes and depends on the type of acoustic wave. For the surface acoustic wave, the enhancement of the optical reaction is greatest at the peak of the resonance, while strain-wave-induced reaction changes of other types of strain waves show their strongest enhancement when the probe pulse is tuned to the wings of the SPP resonance.

In the past decade, EUV lithography has rapidly evolved, and has finally been acknowledged as a requirement for continued scaling. While there have been many improvements on the scanner side to improve resolution, throughput and performance, metrology and characterization have also played a significant role in enabling process maturity and yield. Now, an EUV process owner’s toolbox contains infrastructure and methodology for stochastics-aware process window analysis (SA-PWA), and the subsequent data is a keystone for process transfer to high-volume manufacturing (HVM). However, the monitoring, metrology and analysis needed for SA-PWA is oftentimes at odds with the throughput metrics for HVM. At first, methods for detecting stochastic failures were developed by pushing existing tooling, such as critical dimension scanning electron microscopy (CDSEM), e-beam inspection (EBI) and Brightfield inspection (BFI), outside of its comfort zone to find these nanosized defects at sub-36nm pitch. On one hand, application of these methods improved yield at aggressive sub-36nm pitches. On the other hand, inspections are on the order of hours per wafer or days and the data requires rigorous manual analysis. There are some compromises to improve SA-PWA without sacrificing improvements to yield, but eventually throughput will plateau and become the rate-limiting step in an EUV process development cycle. Continued improvement requires innovative development of next-generation metrology tooling and software components for data analysis, and simplified, or better yet automated, SA-PWA.

Background: Focus-exposure process window measurement and analysis is an essential function in lithography, but the current geometric approach suffers from several significant deficiencies. Aim: By clearly identifying the problems with the Geometric Process Window approach, a new process window measurement and analysis method will be proposed to address these problems. Approach: The Probabilistic Process Window proposed here takes metrology uncertainty into account and rigorously calculates the expected fraction of in-spec features based on settings for best dose/focus and presumed random errors in dose and focus. Using the fraction of in-spec features thus calculated, a much more rigorous determination of the trade-off between exposure latitude and depth of focus can be performed. Results: The Probabilistic Process Window approach is demonstrated on focus-exposure data generated from a standard extreme ultraviolet lithography process at three different pitches, showing the value of this method. Conclusions: The new Probabilistic Process Window approach offers clear advantages in accuracy for both depth of focus determination and best dose/focus determination. Consequently, its use is preferred both for process development applications and high-volume manufacturing.

Background: Stochastic effects stated as the ultimate limit of EUV lithography are widely studied by resist suppliers, mask and metrology tool fabricants. Aim: Although the phenomenon is less explicitly visible, we want to highlight its presence in DUV through variabilities in critical dimension (CD), in shape and in position. These manifestations are not yield killers but may become reliability killers, if combined with some local overlay. Approach: Contour extractions are done from CD-SEM images to enable in-depth computational analysis of the data, to characterize local variabilities, alternatively to massive metrology solutions. This augmented computational metrology multiplies the volume of accessible CD data without requiring any supplementary tool purchasing, as they are already included within conventionally stored SEM images. Results: Contour extractions allowed to detect 5σ deviations from normal law on CD distribution from 1000 images. A set of complementary metrics quantities shape and size uniformities, as well as pattern displacement. It leads to a narrower process window where stochastic effects are minimized. Conclusion: Contour-based metrology offers complementary metrics, useful to characterize or center a process, increasing reliability by doing an extensive analysis of a fair number of CD-SEM images. Are these metrics capable of detecting early signs of process instability?

Algorithms used for e-beam inspection and metrology need to deal with noise, blur, or other distortion sources. For metrology applications such as EUV resist patterns measurement, low electron dosage is desirable to minimize resist damage, as well as to improve turn-around time for massive metrology. However, under low dosage imaging conditions, the SEM images contain a substantial amount of noise and exhibit weak image contrast or blurry features. These factors lead to degradation of measurement precision and accuracy. Advanced image deblurring and restoration methodology becomes crucial to ensure high quality metrology performance. In this paper, we focus on a self-supervised approach to enhance SEM image quality under low dose imaging conditions. Self-supervised approach is highly desirable since it is expensive or sometimes impossible to obtain ground truth data for supervised learning. We demonstrate its capability of enhancing resolution of key features such as pattern edges while reducing the overall noise level. Comparable performance is achieved by enhancing a single frame averaged SEM image and the 4-frame averaged reference image. Performance metrics used for evaluation include CD precision, mean CD and distribution, as well as image quality metrics such as image sharpness, PSNR and SSIM.

Microscopically, a rough surface (or any other feature) can be considered as a set of perturbations from the idealized surface. In reality, the microstructure of such a roughness may include spatial components some being smaller (subresolution) and some larger spatial frequency than the spot size of the SEM, and this should affect SE yields from such a target with respect to an ideal smooth surface. Yet to explore such influences by simulation, Monte Carlo SEM simulations are necessary but quite resource hungry, and thus somewhat limited in ability to include much fine detail, and with SEM simulation codes still being developed to include such effects easily, until now we typically simulate perfect smooth idealized structures. Other examples of such simulation resource-limited simplification of features could be etch halos at base of an etched feature, pits, bumps, craters, scratches or defects on or below the surface, CMP dishing, top corner rounding or footing at the base of a resist line or contact hole, or many other possibilities. We know these will add signatures to the simulated image, but it is important to understand how important are they to achieving realistic results.

The aggressive reduction of semiconductor device dimensions drives many improvements in optical wafer metrology. Currently, chips with device feature sizes below 10 nm are in production which requires robust overlay metrology with sub-nm precision. We will present a compact dark-field Digital Holographic Microscope (df-DHM) that is able to measure overlay on small metrology targets from visible to infrared wavelengths. The coherent amplification and the aberration correction capabilities that is offered by df-DHM allow robust overlay metrology even on weak targets that are covered by absorbing layers. Measured data will be shown that demonstrate the capabilities of this metrology concept.

Overlay is a critical parameter for any semi-conductor foundry, with a direct impact on the fabrication yield, on the quality, and on the performances of the product. Being able to full the overlay constraints has also a direct in influence on the capacity to scale down and to integrate vertically. In addition, the shift of semiconductor applications into more demanding markets such as spatial and automotive leads to higher specifications for the process control. In the semiconductor manufacturing, the overlay is usually measured optically using dedicated targets in the scribe lines. However, targets differ from the product by their dimensions of an order of magnitude larger and by their position up to a few millimeters far from it. This can lead to residual errors and mismatches in the correction sent to the scanner, thus lowering the fabrication yield and the global product quality. For years, many SEM in-device overlay techniques have been published, however they are generally related to new generation of SEM imaging and metrology equipment and require a new dedicated target. In our case, the ambition is to extend the usage of our current CD-SEM tool park. To do so, an on-device and target-free overlay measurement process has been developed. It is based on sub-pixel contour extractions from CD-SEM images and on the use of the design. From a single image, contours of the two layers of interest are extracted from the SEM image and a custom algorithm calculates the overlay as a difference of the realigned design centroids. This dedicated algorithm allows extracting various overlay measurements from one image and enables a production friendly implementation. To evaluate the performances of this method, it has been applied on the patterns of a SRAM with scanner-programmed overlay. The measurements are compared to the conventional optical measurements. On a basis of thousands on-device measurements, the developed method showed a promising 95% rate of successful measurements. Good correlation between the optical model and the CD-SEM measured overlay on the SRAM has been demonstrated, reaching a coefficient of correlation of 0.99 on a pattern where conventional centroid or CD based overlay are limited. Finally, the flexibility of the method to measure various patterns with an ease of recipe creation is shown. Contour-based metrology offers the capability to extract highly valuable information from SEM images while keeping the layers differentiation. The proposed measurement process, being automated and requiring relatively low human inputs is a promising solution for a SEM on device overlay metrology suitable in a high-volume manufacturing environment.

3D heterogeneous integration is an evolving segment of the world semiconductor industry roadmap to enable improvements in device performance beyond Moore’s law expectations. These “More than Moore” (MtM) performance enhancements have the potential for realizing dramatic improvements in communication bandwidth, design flexibility that enables new system architectures on-chip or at the wafer level, and overall cost reduction. 3D heterogeneous integration strives to increase electrical connectivity through pitch and contact dimensional scaling to enable <10μm pitch solder bump scaling, and sub-micrometer hybrid Cu/dielectric fusion bond connectivity. Integration options include wafer to wafer (W2W), pick-and-place (P&P), and die to wafer (D2W) assembly strategies. Enhanced process capability and systems architecture imposes new overlay (OVL) metrology challenges to address variable silicon substrate thickness, stressinduced wafer or die distortions, and tight OVL error specifications. In this work, we will cover the OVL trends and challenges surrounding this evolving segment. We will cover different OVL aspects such as accuracy, measurability, reproducibility, and throughput and discuss their impact on pre and post-bonding error budgets.

In this paper, the rAIMTM (robust AIM) overlay target was investigated in terms of the stability versus the POR AIM® (Advanced Imaging Metrology) target used for imaging-based overlay (IBO) measurement at after development inspection (ADI). The targets were designed using KLA’s MTD AcuRate™, metrology target design software that performs simulations based on the optical properties related to relative permittivity and permeability about the material of each of the layers. Using advanced device layers, we studied the performance of the POR AIM target versus the newly designed rAIM target for imaging-based overlay measurements. For each target, we quantified the optical contrast, kernel signal, correctable modeled terms, total measurement uncertainty (TMU), and overlay (OVL) residuals from the modeled data through various wavelengths inside the Moiré effect regime in the case of rAIM. We demonstrate that there is an OVL measurement performance improvement using the rAIM target versus the POR AIM target. The measured optical properties of the rAIM target and comparison to the POR AIM target will be presented.

With the advent of 45nm and below technology nodes and EUV lithography, the need to identify the chemical composition of defects is of paramount importance. The defects of concern range from 10nm to 500nm, which the current batch of molecular analytical tools cannot address adequately since the indications are that most of the defects detected on photomasks are organic in nature. In this paper, a relatively new nanoscale technique called infrared photoinduced force microscopy (IR PiFM), which combines atomic force microscopy (AFM) and infrared (IR) spectroscopy with ~ 5 nm spatial resolution, is introduced. By utilizing a state-of-the-art tunable broadband IR laser (tunable from ~550 to < 4000 cm^-1 with ~ 3 cm^-1 spectral width over the entire range), truly nanoscale PiF-IR spectra that agree with bulk FTIR spectra can be acquired; PiF-IR spectra can be used to search the existing IR database to unambiguously identify the different chemical species (both organic and inorganic molecules) of sub-20 nm defects and monolayer residues via their IR signatures. PiFM images at fixed wavenumbers associated with the different chemical species provide chemical mapping in real space with ~ 5 nm spatial resolution, clearly illuminating multi-component defects and existence of residues. The paper will show how the nanoscale hyperspectral PiFM data can provide unambiguous and speedy feedback to process engineers engaged in advanced lithography.

We propose a new Magneto-optical Kerr effect (MOKE) system which consists of a dedicated electromagnet and a sensor for inspecting next generation memory, such as Spin-Transfer Torque Magnetoresistive Random Access Memory (STTMRAM). Conventional MOKE system is able to measure a magnetic hysteresis loop at a specific point by detecting the polarization rotation angle with changing the magnetic field intensity with the precision of less than 0.1deg on the reflected light. However, it takes several tens of seconds for measuring each point. We have demonstrated that inspection throughput of more than 1 wafer per hour with 2um pixel resolution can be achieved using proposed method called SCAN MOKE.

The reflective-mode EUV mask scanning lensless imaging microscope (RESCAN) is a synchrotron-based platform dedicated to EUV mask inspection and review at the Swiss Light Source. It is based on coherent diffraction imaging (CDI), which allows retrieving both the phase and the amplitude information of the mask surface. RESCAN has been successfully tested on masks with programmed phase and amplitude defects. A metrology method that can not only detect defects and contamination, but can also determine the material of the defects, can be a powerful tool to help identify the root cause of the defects. Here, we explore the possibility of leveraging the ability of RESCAN to detect the complex amplitude of the sample to distinguish surface defects of different materials. We fabricated a sample with random logic-like absorber patterns and pillar defects on top of a Mo/Si multilayer. We show our experimental results that show the defects of different materials exhibit specific contrast and phase values. This method can be used not only to detect the masks defects but also to identify the defect materials to a limited extent.

We present an automated application for defect detection and classification from ZEISS MultiSEM® images, based on Machine Learning (ML) technology. We acquire MultiSEM images of a semiconductor wafer suited for process window characterization at the imec iN5 logic node and use a dedicated application to train ML models for defect detection and classification. We show the user flow for training and execution, and the resulting capture and nuisance rates. Due to straightforward parallelization, the application is designed for the large amounts of data generated rapidly by the MultiSEM.

A high-throughput e-beam monitoring strategy was developed for capturing advanced DRAM storage node (SN) defects after etching process, when high-aspect-ratio (HAR) structure is involved. With this novel approach, two types of defects, SN-bowing-short and SN-open, were captured with solid signatures. In this study, two wafers with the same structure at different technology nodes,1A and 1B, were used. To enhance the defects signal, back scattered electron (BSE) mode was used to enhance the material contrast for the bottom of HAR holes. With improved BSE image quality, SN-bowing short type was caught using defect detection based on traditional array mode detection. SN-open, however, is more challenging because of its smaller dimension and HAR, resulting in an extremely narrow detection window of image gray level difference between normal storage node hole and the defective one. In order to capture this type of defect, an die-to-database (D2DB) comparison system for e-Beam inspection was applied to address this critical defect and its wafer signature was revealed with extremely high throughput and sensitivity.

Background: Measuring and subtracting SEM noise from a biased measurement of roughness leads to an unbiased roughness measurement. This unbiasing procedure becomes harder as the noise in the image increases. For low image signal-to-noise ratio (below about 2), unbiased roughness measurement becomes less reliable. Aim: It is important to understand the mechanism for the sensitivity of unbiased roughness accuracy to linescan signal-to-noise ratio in order to look for ways to improve unbiased roughness measurement for very noisy images. Approach: Using a combination of mathematical analysis, simulations, and experimental data, the role of pixel size and pitch in the signal-to-noise ratio sensitivity are explored. Results: All evidence points to the correlation of edge detection noise to true edge position as the cause of the errors in unbiased roughness measurement for very noisy images. For small pitch patterns, changes in feature edge position caused by feature roughness changes the linescan slope, which changes the sensitivity of edge detection to SEM image noise. Conclusions: Smaller pixel sizes and larger feature sizes are less sensitive to the signal-to-noise ratio effects described here. For any algorithm used to measure unbiased roughness, the impact of linescan signal-tonoise must be carefully assessed.

ABSTRACT The introduction of new three-dimensional (3D) architectures in future logic and memory devices present new challenges for process metrology and control. Where there is a need to recess only one material type out of a superlattice (SL) layer stack, such structures all have in common the fact that the recess is hidden in the stack. Currently, process control in this field heavily relies on expensive, slow, and destructive metrology such as Transmission Electron Microscopy (TEM). In this work, we use the high voltage Scanning Electron Microscope (SEM) technique in combination with the Elluminator® improved Back-Scattered electrons (BSE) technology for better imaging efficiency to demonstrate the ability to measure cavity recess from top-down SEM images. We present case studies both in logic and memory domains. In Horizontal Gate-All-Around (H-GAA) Nanosheet and Forksheet logic devices, the SiGe layer is recessed in a Si/SiGe SL stack. In 3-Dimensional memory devices, we present results on Poly-Si recess metrology in Poly-Si/SiO₂ SL stack, Molybdenum (Mo) recess metrology in a Mo/aSi SL stack, and TiN recess metrology in a 3DSCM stack used for memory word line. For the evaluation of the proposed recess metrology technique, several wafers with modulated recess amounts were measured using SEM technology at several high voltage landing energies (LE). BSE signal and advanced image analysis algorithms were used to build a prediction model and quantify the recessed amounts using an edge-based analysis. TEM metrology was used to validate the measurement based on the top-down high LE SEM images. We demonstrate that by using high voltage LE, in combination with enhanced BSE efficiency and advanced image analysis algorithms, we can investigate hidden layers in the stack, identify the recessed material edge, and measure accurately the cavities of interest, thus ultimately providing an inline, non-destructive, and statistically representative metrology solution for such advanced technology nodes. This new application will help chip manufacturers to characterize their processes faster and provide an HVM monitoring and control solution.

Metrology challenges surrounding nanosheet structures used in next generation semiconductor devices based around Forksheet and Gate-All-around Field Effect Transistors include procuring measurements in the planar directions, such as critical dimensions, as well as in the vertical direction, such as sheet and recess thicknesses. Subsurface Scanning Probe Microscopy (SSPM) can be used to distinguish and measure features that are buried beneath opaque layers. In this work, we investigate if SSPM can contribute to this challenge and can be used to solve the inverse problem. It is shown that qualitative agreement between modelling and experiments is good, when the experimental contact conditions are sufficient. Quantitative measurements, however, are still out of reach.

Over the past few years, on product overlay (OPO) challenges have become serious yield limiters for the latest technology nodes, requiring new and innovative overlay (OVL) metrology solutions. OVL metrology systems must have excellent measurability capabilities to cover as many different layers as possible, minimize any systematic contribution to measured OVL and demonstrate low residuals and high correlation to AEI SEM and AEI in die overlay (IDO). OVL metrology system manufacturers are required to introduce new target designs, tool hardware (HW) and advanced algorithms to keep up with said challenges. The paper will present optical OVL solutions per segment: foundry, logic, DRAM, and 3D NAND. We will review various new technologies developed in the last year that improve the OVL measurement systems’ performance to meet the above challenges. We will see how the new innovative targets improve measurability and accuracy on imaging-based overlay (IBO) and scatterometry-based overlay (SCOL®). Then, we will review new hardware components designed to improve measurability and overall fleet matching. Lastly, we will discuss how advanced machine learning (ML), multi-wavelength (MWL) and signal-weighting algorithms improve measurability, accuracy, and overall measurement performance.

One of the many constrains of High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL) is related to resist thickness. In fact, one of the consequences of moving from current 0.33NA to 0.55NA (high NA) is the Depth of Focus (DOF) reduction. In addition, as the resist feature lines shrink down to 8nm half pitch, it is essential to limit the aspect ratio to avoid pattern collapse. The direct consequence of such a situation is that a resist thickness of 30nm, usually used for 32nm pitch dense line/space (LS), will not be suitable for 16nm pitch, where the target thickness is expected to be 15nm thickness or less to ensure a similar aspect ratio. The question we need to answer is how the resist thickness reduction will impact the various metrology techniques needed to properly set up a process. To address this question, a set of wafers using both Chemical Amplified Resist (CAR) and Metal Oxide Resist (MOR) at different thicknesses and with different types of underlayer have been generated for LS patterns at 32nm pitch. We first investigated the impact of film thickness by scanning electron microscope (SEM) on the imaging of CAR resist lines. To start with, our current Best-Known Methods (BKM’s) were used to acquire the SEM images. As resist thickness decreases, noise level and image contrast are observed to degrade dramatically. Such an image quality degradation may directly impact the quality of the CD measurements both in terms of accuracy and precision. In this paper we investigated the thin resist wafer set described above using various techniques, such as Critical Dimension Scanning Electron Microscope (CD SEM), Atomic Force Microscopy (AFM), Low Voltage SEM (LV SEM), scatterometry, Pattern Shift Response (PSR), and optical defect inspection. The impact of the resist thickness is estimated for each approach, and optimal settings were investigated to minimize the relative impact on metrology. Our results indicated that, in most cases, alternative operation conditions and BKM settings, sometimes drastically different from the usual operation condition, must be used to guarantee the metrology requirements. Our results show that, despite the impact of thinning resist materials, it is possible to find appropriate settings to strengthen the metrology quality output.

Background: Lithography advancements require resist layer thickness reduction, essential to cope with the low depth of focus (DOF) characteristic of high numerical aperture extreme ultraviolet lithography (HNA EUVL). However, such a requirement poses serious challenges in terms of resist process metrology and characterization, as patterns in thin resist suffer from low contrast, which may affect the performance of the edge detection algorithms used for image analysis, ultimately impacting metrology. Aim: Investigate e-beam imaging using low landing energy (LE) settings as a possible way to address the thin resist film metrology issues. Approach: A low-voltage aberration-corrected SEM developed at Carl Zeiss is to image three thin resist thicknesses and two different underlayers, at various LE and number of frames. All images are analyzed using MetroLER software, to extract the parameters of interest [mean critical dimension (CD), line width roughness (LWR), and linescan signal-to noise-ratio (SNR)] in a consistent way. Results: The results indicate that mean CD and LWR are affected by the measurement conditions, as expected. Imaging through landing energy unravels two opposing regimes in the mean CD estimate, the first in which the mean CD increases due to charging and the second in which the mean CD decreases due to shrinkage. Additionally, the trend between LE and linescan SNR varies depending on the stack. Conclusion: We demonstrated the ability of low-voltage aberration-corrected SEM to perform thin resist metrology with good flexibility and acceptable performance. The landing energy proved to be an important knob for metrology of thin resist.

To understand extreme ultraviolet (EUV) lithography performance of various materials (resists, underlayers etc) or processes (bake, development etc.) in terms of process window (PW) and defectivity, we typically use e-beam based tools (e.g., CDSEM) or optical inspection and defect reviews. The optical inspections can scan large areas quickly to pick up potential defects but give little information about the defect’s morphology. The e-beam inspections provide us with metrology information (CD, PW etc.) and detailed defect characteristics, but is very slow. To connect this gap, i.e., to be able to make high-level projections about process window variations and probable defectivity while scanning small area quickly, we need an intermediate analysis methodology bridging optical inspection and CDSEM analysis. With this objective, we present a new data analysis methodology for understanding process variations and probabilities of developing defects, by performing statistical analysis of the local CD variations for line/spaces patterned using EUV lithography. The local CDs obtained from a CDSEM image are assumed to follow the normal distribution curve. The deviations from the distribution i.e., the outlier local CD data, represent potential bridge and break defects and can help identify the probabilities of obtaining these defects for a process, material, condition etc. The outlier counts are obtained by performing statistical hypothesis testing (e.g., generalized extreme studentized deviate test) of the local CDs. Additional metrics such as p-value of the Shapiro-Wilk hypothesis test for local CD distribution are also measured to quantify the degree of normality of the distribution. Using these metrics, we compared different resists, underlayers and L/S pitches to demonstrate the novel utility of this data analysis method in understanding process variations and finding probable defects. We also demonstrate the validity of this analysis method by correlating the obtained outlier count with the standardized line roughness measurements and defectivity counts.

We present advanced application of novel ellipsometry technique, referred to as self-interference pupil ellipsometry (SIPE), integrating self-interference and pupil microscopy to overcome the sensitivity limitations raised from the conventional spectroscopic ellipsometry. We investigated various samples including a SiO2 monolayer, grating patterned wafers, and DRAM wafers to demonstrate outstanding capability of SIPE for metrology. The angular range corresponds to approximately 5,000 acquisition of conventional ellipsometry tools with 2º angular step scanning. From the experimental results and simulation, we expect the sensitivity of SIPE for structure metrology is at least 0.15 nm at a single wavelength and even better for multispectral measurements.

In this work, a novel spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective measurements of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows focusing on parameters of interest through dramatically simplified optical modelling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are discussed in this paper: monitoring (i) critical dimensions of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) critical dimensions of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy.

A unique challenge has emerged in the Channel Hole process module of advanced 3D NAND manufacturing: control of the lateral silicon nitride recess post Channel Hole etch. A novel mid-infrared critical dimension (IRCD) metrology has been developed on a platform suitable for fab production. Compared traditional optical critical dimension (OCD) technology based on ultraviolet, visible, and near-IR light, the IRCD system exploits unique optical properties of common semiconductor fab materials in the mid-IR to enable accurate measurements of high-aspect-ratio (HAR) etches with high Z dimensional fidelity. Utilizing the mid-IR wavelength range, a robust and unique measurement methodology is demonstrated to measure the lateral silicon nitride recess that occurs post channel hole etch due to etch bias between silicon dioxide and silicon nitride. IRCD metrology is proven to have higher unique sensitivity for lateral silicon nitride recess than other inline non-destructive metrology techniques.

As lithography patterning focus tolerance shrinkage in advanced production fab, defocus due to scanner wafer table or pre-layer contamination has been considered as a yield-loss killer and wafer scrap contributor. Traditionally, we can only apply a fixed by-wafer/by-zone spec to monitor leveling performance, lacking flexibility for further defense system design or root-cause analysis. In this paper we develop a comprehensive solution to capture focus/chuck spot in a high-volume manufacturing environment. This algorithm can automatically detect and categorize defocus spot into focus and chuck spots. Meanwhile, this algorithm produces an overlapped map for back-tracing pre-stage contamination and regularly send an alarm in customized schedule to prevent serious yield loss.

A new generation of metrology tools has been recently released to the market, allowing extensive characterization of semiconductor samples thanks to massive measurements. The resulting substantial growth of measurement sets in size and number of descriptors made the data analysis with the traditional statistical techniques laborious, being unable to consider all data simultaneously. In this work, we propose an analysis method applicable to the massive measurement sets based on a machine learning technique, called Autoencoder (AE). The performance of the original AE model has been boosted in this work thanks to its regularization, by imposing orthogonality of its internal representation and by training only half of the model weights while the second half is deduced. Practically, once the model is trained on the data set of interest, it is used to study relationships between input variables through the chart of the circle of correlations. In this chart, input variables are projected as vectors into the compression plane where the angular distance between them will express their degree of correlation. The representation of massive measurements data through a condensed simple chart that still shows complex interactions between variables is in fact very efficient and facilitating the interpretation of measurements themselves. The experimental validation of the proposed method has been done with measurements of Contact Hole (CH) patterns acquired on samples manufactured with 3 different exposure conditions (underexposure dose, nominal exposure dose, and overexposure dose). The proposed data analysis technique allowed us to clearly identify the impact of the process conditions on patterns characteristics, such as their eccentricity, their geometry, and more. Our results indicated that in case of overexposure, an anisotropic distortion of the CH geometry is present, where 𝑌-axis is the major axis, with larger impact on the pattern surface as compared to the 𝑋-axis. This result has been also confirmed later through defect inspection, where we found that 94% of bridging defects detected occurred along the 𝑌-axis, while only 6% of bridging occurred along the 𝑋-axis. In conclusion, our results indicated that the proposed analysis technique is highly effective for the analysis and interpretation of massive metrology datasets, and that the dimensionality increase of the dataset has a negligible impact on this technique's performance.

In the domain of advanced patterning, and especially at lithography steps achieve very small sizes becomes more and more crucial. This induces measurement challenges and thus requiring the development of new, precise and robust metrology techniques. To overcome the limited constraints of different techniques, one of the most promising approaches is hybrid metrology. It consists in gathering several metrology techniques to measure all the geometrical parameters which are processed them by an algorithm (mainly machine learning algorithm). This work stands out by using for deep learning a multi-branch neural network to increase the precision of predicts. With a particular attention made to the dataset generation and specific settings for each branch, we developed the potential of this approach which increase the precision of predicts.

Historically, the development of high-density ICs has been a series of challenges, and we have overcame them and finally succeeded in mass production. However, the time from initiating product development to mass production is increasing, and moreover, it is taking longer than ever to reach maximum production yields. In this manufacturing environment, reducing development and yield ramping-up time is the most important factor in maximizing productivity and profit, and the key solution for this is MI technology. However, in order to respond to next-generation semiconductor products based on complex 3D structures, MI technology is going beyond the requirements especially for highly localized and non-destructive monitoring of 3D profiles. In this paper, we will discuss the evolutionary direction of these MI solutions. First, we will define the MI challenges that come along with the structural difficulties of new product, and review the changes in technology that have evolved in each field to overcome them. We will also explore the limitations of these technologies and see what new methodologies can be nominated to overcome them. We'll also look at what technical elements are required for HVM and what lessons can be learned from the examples in real production. Finally, we will propose how semiconductor MI technology should change its role through new innovations.

Modern overlay metrology instruments have evolved into systems that provide large amounts of data points (up to 4 overlay targets/sec). Traditionally, this data has been analyzed using models that are based on physically expected parameters. They are typically derived from translation, rotation and magnification (both symmetric and asymmetric) at reticle and wafer level. The resulting coefficients of these models can be directly fed into the scanner to correct overlay errors. As overlay requirements have become more stringent, higher order corrections have been enabled, ultimately leading to corrections-per-exposure (CPE) where no model is used at wafer level. Instead, a different correction at reticle level is allowed for each field. Although this approach has been extremely successful for overlay control purposes, it is increasingly difficult to interpret the resulting models and appreciate the underlying root causes for the overlay corrections as well as for the overlay residuals. This is especially true for new lithographic technologies where all contributors to overlay errors may not be fully characterized yet. In order to gain more insight into the root causes of these overlay errors, we have proposed a model-less overlay analysis technique [1]. In this paper we will apply this method to understand the impact of wafer stack on overlay through wafer heating in EUV lithography. Wafer heating-induced overlay signature is a typical example where the conventional overlay models cannot properly describe the wafer signature and only CPE models can be used to adequately correct. By comparing the signatures of highly reflective (resulting in little wafer heating) with highly absorbing (resulting in more wafer heating) wafer stacks, more insight is gained into the factors that contribute to the overlay corrections.

Aberration is one of the contributors to edge placement error (EPE) variation and overlay error in the scanner system. In the EUV system, aberration-induced wavefront errors can have a much bigger impact than the in a DUV system due to significantly reduced wavelength and heating effect from illumination energy loss through reflective optics. Although in-situ metrology of the scanner system can extract wavefront information accurately and it can be feedbacked for aberration control, dynamic heating effects during long-time full-field exposures and tool-to-tool performance gap by aberration variation in high volume manufacturing (HVM) should be directly monitored on the wafer patterning result for reliable process control. This study aims to identify the feasibility of aberration monitoring on the wafer by using an e-beam metrology tool. Simulation work is performed first for source adjustment and the selection of generic designs of aberration-sensitive patterns of dark field Ta-based EUV masks. For quantitative analysis, the wavefront phase error is directly modulated (dialed-in) in the EUV system, and a wafer is exposed for each modulation condition. The wavefront error induced by the modulated aberration is extracted from measured CD data, using an optical simulation model. We finally discuss the correlation between the extracted aberration and the modulated wavefront error. Based on the result in this work, we investigate the feasibility of the potential application of e-beam metrology on dynamic aberration variation in HVM.

The performance of image-based and diffraction-based overlay metrology depends on the quality of optical signal returning from the buried mark. A desirable class of hard mask materials are the metal-based hard masks. The challenge with metal-based hard masks is that they are typically opaque in the visible range. To enable overlay metrology, a costly process integration scheme replaces the opaque material over the overlay target, while another detects residual topography propagating through the film. Here we discuss the progress towards the fully automated Scanning Probe Metrology tool that combines surface and subsurface channel information in a single image to measure overlay through opaque films.

A recently introduced novel concept ellipsometry, characterized by its unique derivation process of directly extracting the polarization information from the hologram image on pupil plane, has been evaluated experimentally targeting for the application to OCD and overlay tools. With an improvement of splitting the hologram on the pupil, this self-interferometric pupil ellipsometry (SIPE) has gained the capability of measuring all of Stokes parameters (S0-S3) throughout the incident angle of 0 to 72 degrees with omnidirectional orientation. A prototype system incorporating SIPE technology has been fabricated to conduct the performance test with patterned test samples for overlay and CD evaluation, the result of which exhibits the sufficient sensitivity to dimension variation and superior repeatability for practical use. The measurement of thousands of ellipsometric data on pupil only takes tens of milliseconds at the most, realized by leveraging the advantages of self-interferometry that does not have any rotating elements in optics. The experimental result demonstrates the consistency with the simulation results based on TEM data within entire pupil. In the front-line of advanced semiconductor manufacturing, the main obstacles to OCD application, low sensitivity and parameter coupling, have been evaluated, which indicates good prospects with SIPE technology.

High aspect ratio (HAR) structures found in 3D NAND memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep with aspect ratios beyond 50:1 is a particularly challenging process that requires exquisitely accurate and precise control. It is critical to carefully analyze multiple aspects of the etch process, such as hole profile, tilt, uniformity, and quality both during development and production. X-ray critical dimension (XCD) metrology, which is also known as critical dimension small-angle X-ray scattering (CD-SAXS), is a powerful technique that can provide valuable insights on the arrangement, shape, and size of periodic arrays of HAR features. XCD is capable of fast, non-destructive measurements in the cell-area of production wafers, making XCD ideal for in-line metrology. Through several case studies, we will show that XCD can be used to accurately and precisely determine key properties of holes etched into hard mask and multilayer oxide / nitride (ON) film stacks. We show that the measurement of hole tilt can be achieved without the aid of a structural model using a fast tilt methodology that provides sub-nanometer precision. Measurements were performed across several production wafers to determine the etch uniformity and quality. Particular attention was given at the edge of the wafers to account for large variation observed.

Optically opaque materials present a series of challenges for alignment and overlay in the lithography process flow. We demonstrate the efficacy of picosecond acoustic microscopy (PAM) in generating 2D lateral images of structures embedded under opaque layers, including the potential of PAM to generate 3D images by analyzing scanned z planes.

Critical dimension uniformity (CDU) control using dose correction is well established and has relied on traditional polynomial models like Zernike and Legendre for a long time. As process margins are shrinking and CD (and CDU) control becomes a significant contributor to edge placement error (EPE), the dose correction models need to be enhanced to represent the systematic behavior of the fingerprints more precisely. In this paper we show that many CD signatures over the exposure field or over the wafer cannot be corrected efficiently using classical polynomials. As the CD signatures can come from a variety of processes like etch, CVD, polish, or deposition, a flexible model approach is required. Furthermore, making the right decision when choosing the correct model order of the classical polynomial based model is complicated as we need to handle the balance between the degrees of freedom and minimizing the residuals. With this problem statement in mind, we introduce a novel radial basis function (RBF) modeling approach for dose corrections that can correct a wide range of signatures. The new modeling approach is verified on real CD signatures on product, reducing CDU significantly. Additionally, we demonstrate that this approach can make the life of the engineers easy again, as there are no prior decisions about model type and order needed.

Improvements on on-cell overlay is necessary to suppress misalign induced defects. Precise and accurate on-cell overlay measurements are strongly demanded, however, we are facing limitations on conventional CD-SEM based on-cell overlay measurements, such as unexpected overlay bias. To mitigate drawbacks of top view based on-cell overlay measurements, we present voltage contrast based overlay measurements (VCBO) which utilize specially designed cell patterns with combinations of programmed misalignments on scribe lanes, measured by defect inspection equipment, eP5 [1]. We successfully demonstrate the first defect based overlay measurement on DRAM device and a potential of 27% in-die overlay gain is shown. Also, we display overlay process margin at about ~1000 points on wafer. As a definite standard of on-product overlay measurement, this technology will be used for advanced misreading correction (MRC). We believe that the technique would be widely used and become necessary in near future.

State of the art after-develop (ADI) overlay is measured with multi-wavelength micro diffraction-based overlay techniques. A micro diffraction-based overlay target consists of two pairs of gratings, with the same pitch in the top and bottom layer. The gratings in the top layer have a bias offset with respect to the bottom layer in the positive or negative direction. When illuminated, +1st and -1st order light is diffracted. The asymmetry in the intensity of these signals contains the overlay information. In this paper, ADI overlay is measured with a new dark-field target design for ADI overlay. Like a micro diffraction-based overlay target, it consists of pairs of gratings in the top and bottom layer. Instead of a bias offset between top and bottom gratings, different pitches are used resulting in a continuous-bias throughout the grating pair. When illuminated the diffracted light contains moiré fringes, in which the overlay is stored in the phases. This technique has improved accuracy and robustness by design, because it is immune to symmetrical process changes like stack height variations and grating imbalance. Additionally, it shows more stable behavior through wavelength, both in signal strength and overlay. These characteristics make it possible, with a single wavelength, to achieve similar or better performance than micro diffraction-based overlay using a multi-wavelength solution, resulting in higher throughput. This is demonstrated on Samsung’s latest memory node where on average an 21% reduction is achieved in the 3sigma of the mis reading correction with a single-wavelength phase-based overlay measurements, compared to multi-wavelength micro diffraction-based overlay measurements.

At the 3D-NAND analysis site, the variation in the channel hole shape of the entire laminated structure is evaluated threedimensionally by Scanning Electron Microscopy (SEM) to determine the etching conditions in each stacking process. Then, the feedback is given to the stacking process. In other words, quick observation has been required to evaluate the channel hole shape and the layer number accurately in association with each other. The current observation method identifies all the layers by counting manually. However, there is a concern that the observation time will increase due to the miniaturization and multi-layering of devices. As a solution to this problem, we have devised the method to determine a designated layer by joining together Coherence Scanning Interferometry (CSI) and SEM. CSI has capability of nanometerorder height measurement to identify the target layer. To move SEM field of view (FOV) to the designated layer accurately, CSI height map is converted to the XY coordinates of SEM stage by homography transformation. We introduced a new common specimen holder between CSI and SEM to reduce the position error caused by the difference of instruments. Experimentally, the accuracy of XY directional FOV movement in the SEM after coordinate conversion was verified. It was confirmed that the target FOV movement accuracy of 256-layer was achieved by using the common holder. We have the prospect of a new method that can observe the designated layer with high throughput rate because highly accurate data measured by CSI in Z-direction can be acquired.

As semiconductor industry moves to advanced node, capability to well-control On Product Overlay (OPO) becomes a major task force in HVM environment in recent years. In order to continuously sustain OPO at better production level for critical layers, processing on one dedicated immersion (IMM) scanner is a traditional method to meet the quality purpose. However, the tool dedication method impacts IMM scanner throughput and therefore increases cost of ownership for the manufacturing. The ability of smoothly de-stacking the process layers to other IMM scanner without heavily losing OPO performance levels up the full-route productivity, hence enables the cost down opportunity. In this paper, we present a run-to-run APC control methodology and demonstrate the capability to well predict the model terms for inline production scenarios.

In recent years, advances in semiconductor technologies have resulted in the continuous shrinkage of the process window required to fabricate a device, and specifically, the shrinkage of the overall overlay budget of the critical layers. Among other variables, a key contributor of wafer-to-wafer overlay variations is scanner alignment strategy. In high-volume manufacturing (HVM), the reduction in alignment mark count can lead to productivity improvement, however, that tradeoff impacts the scanner alignment layout and overlay model performance. In this paper, we present a comprehensive investigation of an in-line production experiment and simulation results to evaluate overlay performance by cooptimization of scanner alignment mark count, layout for High Order Wafer Alignment (HOWA) model.

The device shrinkage, associated with the latest nodes, comes with tighter overlay budgets. To meet the tighter overlay budgets unconstrained metrology of the device itself is often used to feed the growing complexity of the control loops with dense intra- and inter-field data. ASML’s Self Reference (ASR) In-device metrology has been demonstrated on Front-End-Of-Line (FEOL) and used successfully in High Volume Manufacturing (HVM). In this work we will demonstrate for the first time accurate, robust and reproducible after-etch ASR-based in-device measurement capability for new applications: Active Cut and Storage Node Contact layer. Finding a robust and cost-effective metrology solution is challenging on Active to Active cut, due to low signal strength for any device metrology technology. To be able to measure the overlay of the Active to Active cut currently a special wafer with under-etch is needed, to enhance the contrast. This extra process step and the need for a sacrificial wafer make the approach expensive, difficulty breaking between Critical Dimension Uniformity (CDU) and Overlay, not easier for high order correction and not suitable for HVM. In this work we successfully introduce for the first time the method of ASR-based recipe setup for Active cut layer to remove this extra process step. Middle-End-Of-Line (MEOL) storage node contact layer currently no other after etch measurements are possible at this process step which makes the ASR-based measurement capability even more valuable. The speed and accuracy of this method, combined with an integrated after-development and after-etch control loop, is predicted to bring yield gains over the wafer.

As processes become more complex, and more operations are needed to fabricate individual levels in a sem iconductor chip, the ability to leverage the wealth of information to fully monitor and control the process has become of critica l importance. In this work we extend the application of design-aware fabrication process models to more operations. While one could expect that the process models become more accurate with respect to the target of interest, one of the main benefits of applying this technique is that it further decouples the individual influences that every process step imposes to different designs at different stages of the fabrication process. These results have significant implications on how this methodology can be used to improve process monitoring, a nd in the future extend to process optimization and design specific process control.

Difficulties in availability of important metrology test artifacts is being addressed with a new advanced metrology patterning reticle, AMAG7, which makes available again and updates the suite of key metrology diagnostic and experimental content to the industry previously provided by SEMATECH AMAG. New content covers a broad range of scale regimes from the absolute resolution limits of iArF lithography up to 1um for comparing to larger scales, and including new use cases which have evolved since previous AMAG reticles such as features for contour metrology, EPE, two-level gratings and more. The main grating content of lines, trenches, holes, dots and many variations thereof, is in form of 547 huge 0.8mm gratings measurable by any type of CD measurement tool in discussion in the metrology sector including CD-SAXS with large spot sizes but also by any other tool type with smaller sampling areas, resulting in new IP-neutral test vehicles to enable full open collaboration across the industry. This poster will introduce the newly-designed AMAG7 pattern and demonstrate the achievable lithography and possible test artifacts that can be enabled.

In semiconductor inspection and metrology on scanning electron microscopy (SEM) images, image noise affects the results of inspection and metrology. Image accumulation is effective for denoising but slows image grabbing duration. To get low noise images in high throughput inspection and metrology, we developed a novel denoising algorithm that converts a lowaccumulated image into a clean image like a high-accumulated image. Noise2Noise is one of the image denoising technologies by deep learning for natural images. In this method, clean images are not required for training because the Noise2Noise model is generated with pairs of original images and noisy images created by artificially adding Gaussian noise to the original images. It is more practical than other deep learning methods because collecting clean images is usually difficult. On the other hand, Noise2Noise doesn’t perform enough in SEM images because the noise on the SEM image is not Gaussian noise. To solve this problem, in this study, we analyzed SEM noise characteristics by changing SEM conditions to create the artificial SEM noise. Furthermore, we developed the novel denoising algorithm which is based on Noise2Noise but is specialized to train the artificial SEM noise. We confirmed the improvement of the roughness precision of the proposed method compared to the deep denoise model trained using simple artificial noise. We discuss the impact on throughput advantage of inspection and metrology by applying the proposed method in NGR3500.

Semiconductor manufacturers are increasingly motivated to reduce overlay (OVL) target size. The scribe line area is in high demand, especially as width reduction efforts persist. Furthermore, since overlay control challenges require a higher sampling density, there is a growing need to place ultra-small targets inside the active chip, especially for devices with a large area. One of the main challenges of this new reality is producing smaller cell (grating) sizes to form smaller overlay targets, while maintaining compatible measurements to the standard target size of the same design. To overcome this challenge on typical scatterometry-based overlay (SCOL®) targets, we describe a method developed to perform the preliminary evaluation on a standard cell size of 8μm. This method selects a scalable setup by predicting performance on a 3-5um cell with the same target design (TD) parameters. This allows chipmakers to qualify the OVL measurement during process development on standard size targets, with the confidence that the optimized measurement conditions will be carried over to the smaller targets, saving time and real estate. However, even for scalable designs, target size reduction necessarily forces some size-performance tradeoffs: factors that are negligible for a standard target size can have significant impact on a scaled-down version of the same target design. In this paper we analyze these factors, show how they relate to measurement indicators, and present a method to apply such indicators toward setup selection. For each setup candidate this method can provide predicted performance and measurability as a function of cell size, a powerful tool for target area reduction.

In advanced logic nodes, edge placement error (EPE) budget becomes tighter. Such budget needs to account for items that were nearly negligible before FinFET era, such as rule-based etch bias error or overlay metrology to device (MTD) bias. Some of the new challenges are overlay metrology error due to process induced mark asymmetry, after Etch Inspection (AEI) pattern shift and aberration induced overlay difference between mark and device, all summarized as Metrology to Device bias. YieldStar In-Device Metrology (YS IDM) addresses device-like metrology and real AEI overlay, but in principle might suffer from process asymmetry. In this work we measure ASML Self Reference (ASR) targets by IDM. We use the detected IDM signal to quantify and address for the first time the asymmetry of the printed marks containing device-like structures on FEOL with respect to reference tool. Two main findings characterize this work: - IDM has the capability to identify overlay and tilt signal from a multi-wavelength signal. Scanning electron microscopy (SEM) is a different metrology tool which, to our best knowledge, is instead detecting the two signals as one, without separating them. Overlay and tilt signals identified by IDM can be combined in order to match to SEM - The relative amount of overlay and tilt carried by the IDM signal shows a monotonic and continuous wavelength dependency. These findings increase the understanding of the delta IDM to SEM method, improving the matching between the two. The separation of overly and tilt allows to distinguish which part of the process is causing a certain fingerprint, as tilt is purely driven by non-litho processes. In addition, the combination of overlay and tilt metrology allows improved correlation of the detected AEI signal to yield, and the definition of KPIs for smaller MTD fingerprint. Finally, IDM provides the possibility to keep throughput benefits of optical metrology while overcoming the robustness challenges

Among metrology tools in the semi-conductor manufacturing, critical dimension scanning electron microscopes (CD-SEM) are the most broadly used, especially due to their high resolution, low destructivity, and high throughput. Contour metrology on CD-SEM images has become essential for characterization, modelling, and control of advanced lithography processes. In particular, OPC model’s accuracy can be highly improved using contours metrology. One of the issues when dealing with CD-SEM metrology is that the results are noise sensitive. Moreover, diminishing noise in CD-SEM acquisition leads to resist shrinkage due to exposure time increase. In addition, post-treatment of these shrinkage effects requires compensation algorithms such as artificial intelligence (AI)- driven algorithms, that are another contributor to the error budget of metrology systems. There is thus a need for an accurate, robust to noise, and purely deterministic edge detection algorithm. In this article, we evaluate the benefits of relying on a model-based contour extraction approach for performing measurements. This approach is applied onto both synthetic and experimental CD-SEM images with various patterns (mostly 2D) and noise levels to assess the influence of image integration (frame number) on the contour detection and CD measurement. We demonstrate that a model-based contour extraction algorithm is able to precisely characterize SEM-induced 2D resist shrinkage. We observe that this model-based approach is more robust to noise than standard algorithms by 21% on synthetic data and by 36% on experimental data. Another way of seeing it is, while keeping the same precision, a model-based contour extraction approach can significantly reduce the requested image frame number. The benefits of adopting this approach range from reducing the shrinkage effects to improving SEM image acquisition time. Eventually, no step of shrinkage modelling calibration nor AI-driven image post processing are needed which implies a gain on simplicity and avoids modelling errors.

As the semiconductor industry rapidly approaches the 3nm technology node, on product overlay (OPO) requirements have become even tighter and, as a result, reduction of residual overlay errors have become more important and challenging. Metrology performance enhancements are required to meet these demands. Using angle-resolved pupil imaging, Scatterometry Based Overlay (SCOL®) is a unique overlay metrology architecture that includes massive multi-signal analysis to enable improved accuracy and residuals reduction. In this paper we present a new Rotated Quadrupole (RQ) illumination pattern for SCOL metrology systems designed to enable broad measurable landscape coverage, support additional target design pitches with smaller target dimensions, and improve tool-to-tool matching (TTTM). These improvements enable the SCOL measurement system to provide higher measurement accuracy, reduce residuals error, and improve robustness to process variation. In this paper we will cover theory, some use cases, and measured results.

As 3D NAND advanced technology moves to increasingly denser storage capacity, the film stacks required to create these devices correspondingly increase in quantity and height, creating additional manufacturing and yield challenges. This is especially true for photolithography and specifically for on-product overlay (OPO) control.[1] Multiple sources of process variation impacting overlay need to be considered, controlled, and optimized to yield functional products: complex alignment and overlay schemes, etch tilt effect for deep, high aspect ratio contact etch processes, high order in-die stress overlay, and more. Traditional lithography feedback control is insufficient to cover all these sources of process variation and requires a potentially high Pi-run rate and rework rate, which in turn results in higher costs and lower revenues. Generally, data feedforward is the right solution to handle large lot-to-lot (LxL) overlay process variation. However, as more variation factors interact in the 3D NAND manufacturing processes, a simple feed-forward methodology is insufficient to keep OPO in spec. One critical challenge is that when the alignment and overlay reference layer are not the same, feed-forward will over-correct based on alignment [2]. Further, as other sources of variation may come from different layers and components, feed-forward from only one single layer becomes inadequate for accurate, robust, and optimal OPO control. In this work, we deploy a methodology and corresponding system to provide a feed-forward solution for critical layers. With a workflow from the latest generation 5D Analyzer® data analytics solution, inline OPO is simulated with this new feed-forward strategy. A run-to-run (R2R) system is deployed and validated in a real manufacturing production line. Finally, we observed inline OPO results have improved 50%, and the rework rate has been reduced to < 10%.

In the SADP process, the final spacer line roughness is the key challenge for good pattern transfer. To understand how each process step contributes, the role of roughness in different frequency ranges (Low, Middle, High) is extremely important and it was thoroughly analyzed using unbiased power spectral densities. In this way, it was possible to observe that the deposition step introduces Low to Middle frequency LWR. By tweaking the thin film stress levels during deposition, it is observed that LWR of the final CD of the spacer line can be improved further after the etch step. Applying proper etch step tuning, the etch power condition optimization can reduce line wiggling (responsible for Low frequency LER), while gas flow adjustment can minimize residue from re-deposition (and therefore improve Middle frequency LER). Using the insights in frequency range enabled rapid reduction of LER and LWR by focusing the development methods in both deposition and etch.

Accurate alignment sensors are needed for tight overlay requirements. The interplay of alignment sensor lens aberrations and process variations (such as layer thickness variation or line width variation) can produce position measurement errors. We propose a new method called TIAS (two-beam imaging alignment sensor) where we can achieve high accuracy even in the presence of lens aberrations. It has added benefits of high image contrast and greater depth of focus. We confirmed the aberration robustness of TIAS by our experiment. TIAS technique is not only applicable to alignment sensing but also to image-based overlay (IBO) measurement.

As a part of the semiconductor manufacturing process, an overlay measurement instrument is used to inspect overlay accuracy after exposure. The overlay measurement results are not only used to evaluate accuracy, but also to optimize exposure processing by calculating various offsets based on the measurement results and feeding them back to the exposure system. Increasing the number of overlay measurement points can help identify and compensate for local distortions including EPE (edge placement errors). However, it is not practical to perform overlay measurement for all wafers and all regions, therefore the better strategy for is performing correction through combining predicted results with actual measurement results. Canon is working with Macronix to develop the VMOM (Virtual Machine Overlay Metrology) system for predicting overlay measurement results. The VMOM method uses machine learning to study large amounts of data to derive the relationship between overlay error results and exposure system process variables that cause overlay error. A VMOM model was developed using 3D-NAND process data and overlay prediction accuracy and exposure process optimization were evaluated. This paper reports the development status of the VMOM system and the practical effects of the system.

In advanced lithography, controlling overlay budget is critical, and how to control on production overlay(OPO) quality well as 100% measurement sampling in high volume manufacturing fab will be an impossible mission. Nevertheless, most of HVM fabs encounter with almost the same problem for low sampling lot, wafers, even less measurement points by reason of facility and Fab space issue and cost. No matter how critical overlay need, the advanced process correction (APC) maintaining the overlay performance under 10%~15% lot base sampling with 4 wafers may be the limitation in most of HVM fabs. Base on the 100% measurement conception and possibility, CXMT begin to study ASML cMetro (computation Metrology) possibility through measuring uDBO in Yield Star and combining with scanner leveling information, coming to catch overlay issue wafers and make sure overlay quality as 100% sampling measurement. To achieve this, conventionally, users try to study process possibility in leveling information between with overlay behaviors under the immersion critical layers. To identify the layer strategy and program successful, how to input and build-up cMetro modeling is reasonable and the monitor result is anticipated catching inline overly issue lots under cMetro prediction will be vitally important, no matter going through scanner leveling data method or combining with uDBO measurement as HDOM model. However, this approach will be time-consuming in the beginning due to not only several leveling condition and spilt are necessary, but also need to collect SSO (sampling scheme optimization) or sparse map and high dense map in uDBO measurement. Aiming to speed up the turnaround time, CXMT focus on layers with warpage experience and define the lots & wafers & map sampling to find the correlation. As a results, cMetro HDOM model monitor is possibility to hold up the issue overlay lots even under real inline measurement sampling for 10~15%.

As the technology node shrinks, the systematic defects such as the missing and extra pattern are generated in the process of cell patterning. The defect such as the extra and missing pattern can lead to a critical failure on device. Subsequently, the systematic defect in the UBE could be an etch-gas path on proceeding the etch process and cause the quality degradation of device. In this paper, we propose an automated system to inspect the systematic defect in the cell array with the scanning electron microscope (SEM) image and the physical design. The method consists of conversion, matching, and detection. In the conversion method, the SEM image is converted into the layout using image processing such as noise reduction, segmentation and contour tracing. In the following matching method, gradient descent optimization is used to match the coordinate of layout converted from the SEM image with the coordinate of physical design. In the final detection method, the defect is detected by inspecting the patterns of two layouts. On the test of 2,500 data, we confirmed that the accuracy improved from 97% to 100% as a result of comparing the engineer's visual inspection method with the proposed method. In addition, the turnaround time (TAT) is improved by approximately 40 times. The proposed system is currently applied to DRAM products and used for the field of design for manufacturing (DFM) and manufacturing process.

The random error has been increased relative to the systematic error in overlay misalignment, as the Critical Dimension(CD) of semiconductor-design shrinks to under the 20 nm on DRAM and single-digit nanometer on Logic. The random error comprises diverse factors including non-lithography context, which caused by intricate process other than the scanner itself, hence it’s hard to control through conventional control methods using control knobs of scanner . In this study, we show that how effectively control and reduce on product overlay(OPO) error through making the most use of the conventional control knobs aided by machine learning. In addition to showing improved results, we address that conventional overlay feedback control with weighted moving average(WMA) can give rise to fluctuation of OPO error over entire wafer area, especially on the edge of wafer, due to the lack of control capability or flexibility. As a result, we show that 15.7% of OPO error can be trained and predicted for in-fab data and OPO has been improved from 2.29 nm to 2.08 nm or 9.2% on average over 5-steps of 1,201 lots with simulator.

As device dimensions continuously shrink in semiconductor manufacturing, even tighter overlay control is indispensable to secure good device yield. Using traditional optical overlay metrology via scribe-lane marks it is challenging to achieve good intra-field high-order process correction (iHOPC) due to the limited mark count and uneven mark distribution. Also the scribe-lane based metrology may not fully represent the in-device behavior in some cases. In order to achieve improved accuracy and precision of in-device overlay control, new metrology methodology solution is required. In this paper, three complementary overlay metrology techniques – high voltage scanning electron microscope (HV-SEM), optical scatterometry critical dimension measurement (SCD), and traditional scribe-lane based optical overlay metrology – were adopted for in-device overlay improvement. In 3D NAND device production, in-device overlay measurement is getting more challenging due to the thicker or complex film stack. Though both HV-SEM and SCD are able to measure in-device patterns via capturing buried structures, their different tool principles make them suitable in different situations. Through applying non-zero offset (NZO) overlay compensation at photo exposure, the in-device overlay performance can be enhanced by iHOPC, which is enabled by incorporating high-density in-device sampling measurements from HV-SEM and SCD into traditional optical scribe-lane optical overlay measurements. The improved overlay performance was demonstrated for different process layers in this study.

Overlay is one of the critical parameters and directly impacts yield. Due to high metrology cost, only a small number of wafers are measured per lot. To this end, virtual metrology (VM) aims to provide valuable information about the nonmeasured wafers with little to no additional cost. VM leverages historical per-wafer measurements from exposure tools and processing equipment collected at previous process steps to report overlay on every wafer. As data-driven approaches gain more adoption in the semiconductor manufacturing, machine learning (ML) is a natural choice to tackle this task. In this paper, we present the strategies of learning overlay prediction models from exposure and process context data as well as the steps for achieving desired prediction performance, including data preparation, feature selection, best modeling methods, hyperparameters tuning and objective. We demonstrate our methodology on a large HVM dataset under stable APC conditions.

Critical Dimension measurement in the final slider-level fabrication is essential in the development and manufacture of magnetic read/write heads for hard disk drives (HDD). It validates the device level geometry that plays a dominant role in the magnetic performance of the writer and provides critical feedback to the wafer-level head fabrication process control. Measurement at the slider-level affords the true Air Bearing Surface (ABS) view of the real device that can only be approached by the destructional cross-section at wafer level [1,2]. While the large set of CDSEM images of writer ABS at slider level enables an excellent statistical view of wafer uniformity, it also poses special challenges to the metrology due to a substantial number of variations from the upstream wafer process. The large structure variations observed at the sliderlevel is particularly prevalent in the initial development phase where large DOE (Design of Experiment) are designed to produce intended structure variations, and low process maturity yields large unintended variations among the devices. A traditional metrology used in such a variant data set requires extensive tuning or even a set of separate solutions with each solution in the set only applicable to a small subset of the variations. However, this approach is inefficient and demands high engineer resources. In this work, we use a machine learning based metrology approach to process the large set of magnetic writer device images at the slider level. For the current study, we use a model-based solution that was trained with deep learning (DL) using a dataset from 4 different head designs. The model aims to retrieve precise boundaries of the head to perform accurate measurements. We demonstrate the progressive robustness of the model-based solution by expanding the training set to measure the CD of writer poles with different designs and large process variations due to the intrinsic wafer level structure variation and the image distortions from the slider fabrication process. In addition, we will demonstrate the efficiency of the Deep Learning (DL) based solution in comparison with traditional metrology and manual measurements on the same set of data.

In order to achieve pattern shrinkage of the memory device, the manufacturing process is getting more complicated and the production period is getting longer. Therefore, the methodology of predicting fab-out electrical die sorting (EDS) test results from in-fab metrology (CD, Optical CD, Thickness, etc.) data is becoming increasingly important. In this study, we propose a novel methodology to improve the fab-out EDS prediction of memory device with in-fab metrology data. Since fab-out EDS results of memory device are binary data consisting of pass or fail at the chip level, indices based on binary classification are suitable for verifying correlation between in-fab metrology data to fab-out EDS results. However, in memory device production, the number of pass chips is much larger than that of fail chips. So in this case, the data imbalance of the pass/fail chip ratio in memory semiconductor production can lead to distortion of binary classification indices such as accuracy, precision, recall, and F-score. We modified the accuracy equation of binary classification to compensate for distortion of binary classification indices due to data imbalance, allowing us to determine chip-level in-fab production specifications (specs) more accurately. We also confirm that the fab-out EDS prediction error has decreased 37.5% when using new in-fab production specs determined by our effective accuracy equation.

Circuit designs are becoming denser and more complex in advanced semiconductor process technologies. The foundry process windows are becoming smaller and smaller which increases sensitivity to wafer surface defects. These defects should be detected early to resolve the root causes and eventually help to improve the yield. Wafer defects are still often inspected manually while the defect counts can reach into the millions. It takes a long time to analyze and review the results while the identification of the root causes may be less accurate and buried in noise. In this paper, UMC advance research teams, in collaboration with the Cadence DFM team, utilized the Pegasus Computational Pattern Analytics (CPA) software to develop an enhanced inspection flow. This flow includes defect data preprocessing, classification, filtering, and reduction of huge data volumes to create visible and easy to review results. By finding more accurate root causes, we could reduce process develop time and finally improve wafer yields.

A variety of middle-of-line lithography overlay (OVL) and process window (PW) parameters have been monitored using PDF Solutions Design-for-InspectionTM (DFITM) in 14nm FinFET technology. The DFI system, which incorporates voltage contrast (VC) electron beam (e-beam) technique on PDF Solutions knowledge based test structure designs, has proven to assist lithography overlay control and process diagnostics, covering process loops of epitaxy, metal gate (MG), contact on active (M0A), contact on metal gate (M0P) as well as segmentation cuts of M0A and MG. In-line eBeam scans are performed after Contact CMP, and OVL and PW parameters are extracted from the curve fitting of VC signals responding to misalignment values. For each process module, dedicated test structures with different layout attributes are designed and placed on the wafer to characterize OVL and PW sensitivity to feature density, geometry and substrate doping. In this work, the concept of DFI system, with specific illustration of DFI M0A to MG OVL measurement to assist inline OVL control and process fix is reported. Although eBeam-based Voltage Contrast techniques traditionally have been used to detect Open and Short failures, and cannot be used to directly measure critical dimensions (CD) of patterned features, the DFI system is designed to monitor integrated process window (PW) variation introduced either by an intentional process split or an unintentional process/tool drift in production line. The results presented below demonstrate DFI capability to assist in-line OVL and PW control for yield enhancement, production monitoring, and excursion prevention.

Understanding contributors to critical dimension uniformity (CDU) is becoming ever more important. We propose a systematic CDU breakdown into contributions that can be attributed to local CDU, intra-field CDU, field-to-field CDU, intra-lot CDU and lot-to-lot CD variations using smart metric definitions. We checked the CDU breakdown on synthetic data as well as on real DRAM production data. Comparing our CDU breakdown to results from nested ANOVA made with statistical software packages, we could verify that the results were very close, while our calculation method was orders of magnitude faster.

Predicting the best preforming overlay marks for a set of layers in a new technology process flow would provide a powerful tool, which could potentially streamline the time consuming measurement process search for the optimal overlay mark. This is challenging because integration of the next generation of transistors and interconnects is becoming increasingly complex, so evaluating overlay mark performance in isolation yields partially valuable results. We show how process emulation can be used to evaluate overlay marks in conjunction with optical simulations for the critical patterning levels, and only the marks that perform well in simulation are allowed on the final mask, thereby predicting the best overlay marks for a particular technology. To make this methodology useful, it is important to cater each analysis to the specific materials being used, their optical properties, and the integration scheme of the technology. This is done as follows: (a) the optical properties of the materials being used are extracted using standard metrology tools, (b) the process flow of an existing technology is emulated, (c) an initial optical model is created with the inputs for settings like wavelength and focus form the metrology tool configuration, (d) the images from the overlay tool for the existing technology are analyzed to calibrate for unknowns such as numerical aperture and coherence, and finally, (e) the calibrated model is used on future technology flows to evaluate the performance of overlay marks. We will illustrate the validity of this methodology using specific examples and highlight its predictive capability.

In recent years, the 3D NAND stack has continued to expand rapidly in the Z direction with tighter process windows, while deck-to-deck overlay faces increasing measurability and accuracy challenges. Meanwhile, thick opaque hard mask (HM) has been utilized in several layers, thus downgrades a lot of mark contrast and introduces large process variation (PV). To meet tightened overlay requirements, KLA’s Metrology Target Design (MTD) assisted by simulation analysis has become an important part of the holistic overlay improvement solution set. Compared to the conventional target design simulation process in which the target stack is built up with a standard template, in this work, a customized template was designed to fit actual mark behavior. Using this new template, more accurate simulation to measurement (S2M) matching was demonstrated, which makes the new target design more reliable. With this added benefit, the newly designed target achieved desirable residual improvement with better on-product overlay (OPO) performance. In the case of the challenging thick opaque HM layer, target segmentation and CD/Pitch optimization by simulation also significantly improved mark contrast and OPO using the newly designed mark. Along with contrast gain, the robustness against large PV of the simulated mark was increased by quantifying comprehensive PV on product wafers. Furthermore, with the verification of the measured data, simulation data can be used to establish a more thorough representation of the process characteristics and parametric sensitive virtual metrology, targeted to meet the goals of maximizing overlay accuracy in the 3D NAND process.

In scanning electron microscope (SEM) image simulation, it is necessary to consider the charging of electron beam irradiation, which can be computationally intensive. Therefore, we have developed a neural network-based algorithm to generate SEM images by inputting the shape and material properties of semiconductor devices, after which various preprocesses are applied to the physical parameters to improve the accuracy. The contrast and visibility of the generated images are then compared with simulation results that are not included in the training dataset. As a preliminary result, we found that the physical parameters that affect charging, such as the relative permittivity and electron mobility of the material, can be predicted. The effect of acceptance is also considered in the training process to reproduce the changes in image quality depending on the type and arrangement of detectors.

Overlay metrology plays a significant role in process and yield control for integrated circuit (IC) manufacturing. As the On-Product Overlay (OPO) in advance nodes is reduced to a few nanometers, a very small margin is left for measurement inaccuracy. We introduce a multi-wavelength (spectral) analysis and measurement method, capable of characterizing overlay inaccuracy signatures on the wafer, and quantifying and removing the inaccuracy portion of the overlay measurement, resulting in a more accurate measurement, better process control, and yield enhancement. This method was applied to SK hynix’s advanced process production wafers, demonstrating an enhancement in accuracy over single-wavelength based overlay measurements.

A double patterning Litho-Etch-Litho-Etch (LELE) process developed in a test vehicle for Back End of Line manufacturing is investigated using rigorous, physics-based three-dimensional computational models. The wafer topography consists of TiN, SiO2, Spin-on-Carbon, Spin-on-Glass (SOG), over which the photoresist patterns are printed. The lithography step of the LELE flow is simulated using PROLITH, and the etching steps are simulated using ProETCH, a new dry etch simulator developed at KLA. Two clips that are spatially close to another and present in the photomask layout for the first and second lithography steps are considered to investigate the impact of etch process conditions on etch bias. We found that the final etch bias during the LELE processes is dominantly induced during the etch of SOG. The tapered profiles induced during the SOG etch process are due to the polymerization by CFx radicals produced in the plasma. The effect of varying the neutral-ion-flux ratio on the etch bias is investigated. Etch process development for SOG needs to balance multiple targets to avoid defect formation.

It has long been understood1 that in photolithographic mini-environments, acetic acid reacts with residual ammonia to form salts that cause haze formation on the scanner optics. It also induces cosmetic defects (satellite defect) on the surface of the photoresist. The acetic acid is generated in multi-function chemical filters, where PGMEA (a photoresist solvent) undergoes hydrolysis in the acidified media used to remove bases, producing PGME and acetic acid. Acetic acid is difficult to measure in the gas phase at parts-per-billion levels, requiring either costly and cumbersome mass spectrometers that are unsuitable for deployment in a production environment, or ion chromatography, a labor-intensive, off-line technique commonly performed off-site by a third-party analytical services lab. In this manuscript, we report on a novel AMC monitoring solution for measuring acetic acid, PGMEA, PGME, NH3, and other VOCs (volatile organic compounds). The heart of the system is a real-time laser-based analyzer based on a new analytical technique called Broad Band Cavity Ring Down Spectroscopy (BB-CRDS). The VOC monitoring system has several features which make it well-suited to AMC measurements in the production environment: ultra-trace measurements of a variety of VOC species; 24/7 operation without user intervention; little to no consumables; unparalleled accuracy without the need for calibration. The AMC system also consists of a high performance 8-port multiplexer, monitoring the photolithography bay at STMicroelectronics - Rousset fab. Here we report on acetic acid and PGMEA levels observed in several track tool and scanner minienvironments, over a period of several months.

In modern DRAM processes, there are some critical layers that are particularly challenging for overlay (OVL) control. The conventional method of metrology target design for these challenging layers is to verify target performance using simulation based on the specific, final device process. After full simulations, target measurability issues can be encountered where the limited, available solutions (open hard mask, create topography, etc.) are costly and high risk. However, in DRAM new product R&D, there is always some tolerance for process tuning. The use of virtual Archer™ OVL measurements in metrology target design (MTD) can simulate metrology performance for these potential process splits, helping to find a good balance between process options and metrology performance. A significant improvement in target contrast for imaging-based overlay (IBO) is demonstrated by simulation on one of these challenging layers after process optimization as compared to the baseline (BSL) process. In this paper we will present the virtual MTD detailed flow and design considerations to achieve an optimized process and target design. The contrast of a key performance indicator (KPI) is improved by more than 30%, enabling OVL measurability of the challenging layer in new processes.

There is widespread recognition in the industry that as the design rule decreases, the number of airborne molecular compounds that can drive defect formation is increasing at an exponential rate [citation: IRDS 2020]. The vast majority of these new critically important AMCs are volatile organic compounds. These VOCs are difficult to measure in the gas phase at the parts-per-billion and parts-per-trillion levels that are needed for the tight process control requirements of advanced design rules. In this paper, we report on a novel AMC chemical metrology solution for measuring critical VOCs that are relevant to the photolithography cell. The heart of the system is a real-time laserbased analyzer based on a new analytical technique called Broad Band Cavity Ring Down Spectroscopy (BB-CRDS). The VOC monitoring system has several features which make it ideally suited to AMC measurements in the production environment: ultra-trace measurements at ppb levels without the need for calibration, 24/7 operation without user intervention, and negligible consumables. The analyzer was integrated into a state-of-the-art multiplexer to monitor ten VOC species in the photolithography cell in a modern semiconductor fab. We report on multiple observations made, including transient solvent leak events, multifunction chemical filter performance, and baseline characterization of AMCs inside track tools.

As the development technology of 3D NAND advances, it becomes increasingly important to measure the mid and bottom profiles of High-Aspect Ratio(HAR) hole or line structures. To estimate the HAR structure profile, SEM is generally used to measure the bottom CD using a high acceleration voltage, but there are cases where the measured CD does not represent actual bottom CD of the structure. To solve this problem, we propose a method of inferring the actual depth at which the measured CD is located by examining the CD change according to the change in the accelerating voltage of the electron beam and the inclination of the incident beam. After inferring the CD measured from the actual hole and line structure, the method was validated on samples with geometrically known structures. It is expected that the method approached in this paper can be used for 3D microstructure measurement using SEM technology in the future.

PDF’s electrically testable structures, called Characterization Vehicles™ (CV’s), have been extremely successful in characterizing printability windows of the leading- edge technologies for the last 15 years. We have been able to demonstrate clear correlations between the electrical misalignment data and product yield for several technology generations and these CV’s have been employed in all leading foundries. However, their placement is limited to the scribe lines and in many fabs they are tested only at the end of wafer processing. We have conducted many experiments that demonstrated their accuracy vs. the cross-sectional TEM and concluded that the final edge placement error (EPE) does not always correlate to in-line overlay measurements, and often exceeds by far the allowable tolerances, leading to the product yield loss. With the multiple patterning schemes and recently EUV, there is a clear need to fully characterize the EPE budget in the technology development and, if this information is available in-line, use this information for process control by feeding it back to the scanners. Over the last 8 years a new technology called Design For Inspection™ (DFI) has been developed and already proven in all major foundries. Specially designed test structures are placed within the product die in place of the filler cells and dummy fill without any area penalty, as well as in the scribe lines, which allows for the EPE monitoring with sub-Design Rule designs. All DFI structures are tested with a custom (designed and manufactured by PDF) eBeam voltage contrast tool with a very high speed and sub-nm resolution for the EPE characterization. The new vector scan eProbe-250 tool is capable of testing billions of DFI structures sites with a speed up to 5 billion sites/hour on a single wafer. Contrary to the typical eBeam machines, it utilizes the gray scale data from the tool to allow for the marginality extraction (soft failures which may have significant reliability impact). This allows for extensive Design of Experiment (DoE) to be performed to fully characterize the EPE and other process marginalities. This DFI methodology has been enthusiastically received by not only foundries but also leading fabless companies and more than 20 tape-outs of MultiProduct Wafers (MPW’s) and actual product wafer scribes have been already executed proving the value of this methodology from the 14nm down to 5 nm nodes. This methodology has been currently applied to the EUV characterization where the overlay and local LER variations contribute the most to the EPE budget.

Airborne chemical contaminants (AMCs) in the lithography cell are responsible for yield-impacting issues such as scanner haze and wafer defects. Detecting and monitoring these chemicals in real-time is critical in IC fabs. Many technologies have been deployed to monitor AMCs, but many of them are not production-worthy solutions that meet the stringent sensitivity and throughput requirements driving Moore's law. Here, we demonstrate a fully integrated AMC monitoring system, Picarro SAM (Sample. Analyze. Monitor.), that detects a variety of chemicals in real-time from multiple locations in a lithography cell. Multiple scanners, track tools, and reticle stockers are monitored 24X7 for excursions of critical inorganic AMCs such as hydrochloric acid, hydrofluoric acid, ammonia, and sulfur dioxide, as well as volatile organic compounds such as acetic acid, PGMEA, NMP, siloxanes, etc. that impact the performance of the lithography process. The SAM system integrates sensors based on Cavity Ring-Down Spectroscopy (CRDS) with a high-performance sampling system. While CRDS is an established technology to detect critical inorganic AMCs, here we demonstrate the ability to measure several critical VOCs using a new technique called broadband CRDS. SAM monitors contaminants in various parts of the scanner and track with multiple sampling tubes extending to a hundred feet or more to accommodate remote areas of the process tool. The SAM system is a fast, easy-to-use, production-ready analytical tool to monitor trace VOC and inorganic contaminants in the parts per trillion to low ppb range within seconds that helps engineers take corrective actions much faster than ever before.

Current best practices for the extraction of critical dimensions (CDs) from microscopic images requires semiconductor process engineers to analyze images one by one, which is tedious, prone to human bias, time-consuming and expensive. Automated CD extraction using machine learning methodologies is an approach to accelerate and improve the accuracy of this process. Deep learning convolutional neural nets specifically can be used effectively for image segmentation and identification of different material regions; however, providing enough annotated data for training and testing is an ongoing challenge. Here, we demonstrate a method where only one sample image is needed for the neural net to learn how to extract the CDs of interests. The methodology is specifically demonstrated for extracting CDs from a metal assisted chemical etching process. Each experimental SEM image is automatically measured in about 45 seconds. The extracted CD measurements are within 4 nm (<5% error) of the human measured CDs. This automated extraction enables process engineers to improve the accuracy of their metrology workflow, reduce their total metrology costs, and accelerate their process development.

The metrology FOUP (M-FOUP) is a self-contained metrology tool in a wafer carrier. This metrology concept, which was designed and manufactured by SEMILAB, is actively being evaluated in GLOBALFOUNDRIES. The M-FOUP system consists of a controller (MCONTROLLER), which controls multiple M-FOUP measurement units. Each independently operated M-FOUP unit utilizes a multi-point spectroscopic reflectometry technique, which can be used for many thickness applications. The self-contained metrology device has advantages over traditional film thickness measurement tools including reduced cost, significantly smaller footprint, and increased availability. In a previous article we focused on the technical details of the M-FOUP unit such as the overall design, the temperature distribution, charging/discharging routine, typical spectra, and typical wafer map. The focus of this work is on integrating the M-FOUP system into a semiconductor fab environment. This requires a high-level orchestration of multiple fab systems including the automated material handling system (AMHS), real-time dispatching (RTD) system and the MFOUP system itself. The management of the metrology jobs and data collection using M-FOUP from a point of view of Manufacturing Execution System (MES) are discussed.

In a leading-edge high-volume manufacturing fab, lithographers focus on searching for a suitable alignment layout strategy to cover process-induced overlay variation. However, how to minimize scanner cross-chuck overlay impact also draws attention due to WPH loss from chuck dedication. In this paper we evaluate a novel algorithm to analyze lithography scanner process/metrology data and introduce a new KPI called “model accuracy” for alignment sampling layout strategy creation, which takes into account robustness index as wafer-to-wafer/chuck-to-chuck variation. Combined with simulated overlay performance, an optimal alignment layout strategy is recommended for a maximum coverage of cross-chuck overlay, which leads to maximum productivity.

One of the most critical challenges in the lithography process is to effectively control all critical patterns over the full exposure field, across wafer, and from lot to lot consistently. ASML’s advanced dose-control solutions have been widely adopted to control CDU of critical patterns. A new high-order dose-control capability is introduced with extended controllability over a larger number of patterns to mitigate the stochastic effect and optimize dies-in-spec performance. Traditionally, designed marks or patterns are placed in the die for dense metrology sampling required for the advanced high-order dose-control applications. However, this method has a few disadvantages especially for logic foundry use cases. For example, the designed marks are often not identical to random logic critical patterns, thus leading to a situation in which marks are controlled well while device patterns are not. In-die placement of the designed marks normally imposes constrains in device layout, which is not acceptable in some cases such as large-die layouts. A preferred approach would be to measure directly on device-critical and/or weak-point (WP) patterns. But this brings up another challenge in metrology of device WP patterns. With conventional CDSEM the amount of data points is limited by the tool throughput. WP patterns are typically 2D patterns, with normally a high noise contribution from local variations (due to resist stochastics) and metrology. Thus to suppress the local variations, averaging of many local measurements of 2D WP patterns is preferred. This requires a high throughput e-beam metrology tool capable of making massive amount of inline measurements within a given cycle time. To address these challenges, we have developed a method of using yield-limiting device patterns to directly control dose and thus improve CDU. Close to 100 WPs per in-die location have been selected with a dense die coverage to minimize the contribution to global CDU from the local variations and metrology noise. A high-speed e-beam metrology tool is used to measure all the selected WP patterns. A CDU budget breakdown (BB) has been analyzed to identify and quantify CDU contributors, such as reticle fingerprint, OPC error, local CDU, metrology noise, etc. Different in-die WP sampling and dose-control methods are studied in this work to achieve optimal CDU correction while keeping the metrology cycle time under control for HVM implementation.