The 'what is the requirement?' aspect of advanced computing and how it relates to and supports Air Force space-based operations is a key issue. In support of the Air Force Space Command's five major mission areas (space control, force enhancement, force applications, space support and mission support), two-fifths of the requirements have associated stringent computing/size implications. The Air Force Research Laboratory's 'migration to space' concept will eventually shift Science and Technology (S&T) dollars from predominantly airborne systems to airborne-and-space related S&T areas. One challenging 'space' area is in the development of sophisticated on-board computing processes for the next generation smaller, cheaper satellite systems. These new space systems (called microsats or nanosats) could be as small as a softball, yet perform functions that are currently being done by large, vulnerable ground-based assets. The Joint Battlespace Infosphere (JBI) concept will be used to manage the overall process of space applications coupled with advancements in computing. The JBI can be defined as a globally interoperable information 'space' which aggregates, integrates, fuses, and intelligently disseminates all relevant battlespace knowledge to support effective decision-making at all echelons of a Joint Task Force (JTF). This paper explores a single theme -- on-board processing is the best avenue to take advantage of advancements in high-performance computing, high-density memories, communications, and re-programmable architecture technologies. The goal is to break away from 'no changes after launch' design to a more flexible design environment that can take advantage of changing space requirements and needs while the space vehicle is 'on orbit.'

This paper presents some simulation results of the evolution of 2D visual pattern recognizers to be implemented very shortly on real hardware, namely the 'CAM-Brain Machine' (CBM), an FPGA based piece of evolvable hardware which implements a genetic algorithm (GA) to evolve a 3D cellular automata (CA) based neural network circuit module, of approximately 1,000 neurons, in about a second, i.e. a complete run of a GA, with 10,000s of circuit growths and performance evaluations. Up to 65,000 of these modules, each of which is evolved with a humanly specified function, can be downloaded into a large RAM space, and interconnected according to humanly specified gvdvips -o SPIE-2000.ps SPIE-2000 artificial brain architectures. This RAM, containing an artificial brain with up to 75 million neurons, is then updated by the CBM at a rate of 130 billion CA cells per second. Such speeds will enable real time control of robots and hopefully the birth of a new research field that we call 'brain building.' The first such artificial brain, to be built at STARLAB in 2000 and beyond, will be used to control the behaviors of a life sized kitten robot called 'Robokitty.' This kitten robot will need 2D pattern recognizers in the visual section of its artificial brain. This paper presents simulation results on the evolvability and generalization properties of such recognizers.

Teraflops-scale computing systems are becoming available to an increasingly broad range of users as the performance of the constituent processing elements increases and their relative cost (e.g. per Mflops) decreases. To the original DOE ASCI Red machine has been added the ASCI Blue systems and additional 1 Teraflops commercial systems at key national centers. Clusters of low cost PCs employing COTS network technologies (e.g. Beowulf-class systems) will make peak Teraflops performance available for less than 2M in the near future for certain classes of well behaved problems. Future larger systems include the Japanese Earth Simulator with a peak performance of 40 Teraflops and three larger ASCI systems anticipated to provide peak performance of 10, 30, and 100 Teraflops culminating in 2005. These systems use existing or near term conventional technologies and architectures with some specialized integration logic and networking. While the peak performance goals can be satisfied through this strategy over the next decade, two major challenges confront the high performance computing community: (1) how to aggressively accelerate performance to the operational regime beyond a Petaflops, and (2) how to achieve high efficiency for a wide range of applications. The Hybrid Technology Multithreaded (HTMT) computer is under development by an interdisciplinary team of investigators to address both problems through an innovative combination of advanced technologies and dynamic adaptive architecture. This paper describes the strategy embodied by the HTMT architecture and discusses the key factors that may enable it to achieve two to three orders of magnitude performance with respect to today's largest systems at a cost and power consumption of only a factor of two to three times those same present day systems.

Optical signal processing and computing was triggered by the invention of the laser. Starting practically in 1960, it really took off with the introduction of the spatial matched filter in 1964. About 36 years later we are still far from extensive use of optics in traditional computing systems. In this presentation we shall overview the developments during these 40 years and discuss the advantages, disadvantages and limitations (fundamental as well as technological) of optics for this application. Extending the concept of computing and introducing the notion of Application Oriented Computing, we demonstrate that optics already plays an important, and rapidly growing role in advanced computing paradigms, although in a different way than it was initially anticipated.

A review is made of some of the Microsystems Laboratory research on new classes of computers. These are broken into four classes, number based, group theory based, wave based and biologically based, and include Fibonacci, p-adic, elliptic curve, permutation, soliton, microfluidic, neural type, neuron chip, and protein based computers. A table is included in which each class is summarized.

An emerging computing paradigm is presented bridging the gap between many novel technologies using photons, electrons, and molecules for signal processing. Computing with waves is the essence of the analogic cellular computer, having elementary instructions as PDE solvers on a grid. The formal computer architecture, the CNN Universal Machine, has been implemented in CMOS, in optical and in molecular level technologies. The standard CMOS implementation is a single chip visual microprocessor with TeraOPS speed. The heart of the matter is described by a formal framework where the data are flows. The only discrete entity is the space. Recent developments as well as the computational infrastructure are briefly summarized.

NRL is developing compact optic flow sensors for use in a variety of small-scale navigation and collision avoidance tasks. These sensors are being developed for use in micro air vehicles (MAVs), which are autonomous aircraft whose maximum dimension is on the order of 15 cm. To achieve desired weight specifications of 1 - 2 grams, mixed-signal VLSI circuitry is being used to develop compact focal plane sensors that directly compute optic flow. As an interim proof of principle, we have constructed a sensor comprising a focal plane sensor head with on-chip processing and a back-end PIC microcontroller. This interim sensors weighs approximately 25 grams and is able to measure optic flow with real-world and low-contrast textures. Variations of this sensor have been used to control the flight of a glider in real-time to avoid collisions with walls.

Computation in artificial perceptual systems assumes that appropriate and reliable sensory information about the environment is available. However, today's sensors cannot guarantee optimal information at all times. For example, when an image from a CCD camera saturates, the entire vision system fails regardless of how 'algorithmically' sophisticated it is. The principal goal of sensory computing is to extract useful information about the environment from 'imperfect' sensors. This paper attempts to generalize our experience with smart vision sensors and provide a direction and illustration for exploiting complex spatio-temporal interaction of image formation, signal detectors, and on-chip processing to extract a surprising amount of useful information from on-chip systems. The examples presented include: VLSI sensory computing systems for adaptive imaging, ultra fast feature tracking with attention, and ultra fast range imaging. Using these examples, we illustrate how sensory computing can extract unique, rich and otherwise not obtainable sensory information when an appropriate balance is maintained between sensing modality, algorithms and available technology.

The design, characterization and evaluation of CMOS based silicon photodetectors/photoreceivers suitable for smart-pixel based applications are presented. Implemented with a conventional CMOS fabrication process, these photodetectors/receiver circuits can be reliably fabricated for smart-pixel based photonic information processing systems that combine the parallelism associated with optics and the data processing capabilities associated with CMOS logic. Several different CMOS based photodetector structures including p-n junction detectors and bipolar phototransistors are presented. Simulation results indicate that the p-n junction detectors will provide photocurrents in the range of nanoamps with rise/fall times on the order of picoseconds. Although slower response is expected with the phototransistor structure, the optoelectronic gain increases the photocurrent to the microamps range. In addition to fabrication and evaluation of individual photodetectors, we present the design and evaluation of high gain photoreceiver array. Based on a standard 1.2 micrometer CMOS fabrication process the monolithic photodetector/receiver circuit includes a bipolar phototransistor, a three-stage current amplifier and a differential amplifier that produces output at digital logic levels. The photoreceiver with high gain and adjustable threshold has a wide dynamic range. For a reference voltage of 3.2 V, the optical power threshold has been measured at less than 1 nW. A page-oriented optical data detection is demonstrated using a 5 X 5 smart-pixel photoreceiver array.

Traditional robotics revolves around the microprocessor. All well-known demonstrations of sensory guided motor control, such as jugglers and mobile robots, require at least one CPU. Recently, the availability of fast CPUs have made real-time sensory-motor control possible, however, problems with high power consumption and lack of autonomy still remain. In fact, the best examples of real-time robotics are usually tethered or require large batteries. We present a new paradigm for robotics control that uses no explicit CPU. We use computational sensors that are directly interfaced with adaptive actuation units. The units perform motor control and have learning capabilities. This architecture distributes computation over the entire body of the robot, in every sensor and actuator. Clearly, this is similar to biological sensory- motor systems. Some researchers have tried to model the latter in software, again using CPUs. We demonstrate this idea in with an adaptive locomotion controller chip. The locomotory controller for walking, running, swimming and flying animals is based on a Central Pattern Generator (CPG). CPGs are modeled as systems of coupled non-linear oscillators that control muscles responsible for movement. Here we describe an adaptive CPG model, implemented in a custom VLSI chip, which is used to control an under-actuated and asymmetric robotic leg.

The recursive use of thresholded binary networks of the Hopfield-type lead to the efficient retrieval of the regularized least-squares (LS) solution in certain inverse problem formulations. This strategy is especially effective when substantial data must be processed by resources which are constrained either in space or available bandwidth. Partitions of the network are identified based on forms of representation of the data. The objective criterion is optimized using sequential and parallel updates on these partitions. The algorithms consist of minimizing a suboptimal objective criterion in the currently active partition. Once the local minima is attained, an inactive partition is chosen to continue the minimization. An application to digital image restoration is considered.

Present day neural net and connectionist models of the cortex have not been effective in duplicating higher-level brain function and specially the ability of the cortex/brain to process dynamic input patterns. Using mathematics quite- different from that used in the transfer-function and stimulus-response approach to collective nonlinear processing used in conventional networks, we describe here progress with a novel approach to modeling the cortex that combines concepts and tools from nonlinear dynamics and information theory that offers a radically new way to process, classify/learn and recognize spatio-temporal signals.

We present a model of computation with ordinary differential equations (ODEs) which converge to attractors that are interpreted as the output of a computation. We introduce a measure of complexity for exponentially convergent ODEs, enabling an algorithmic analysis of continuous time flows and their comparison with discrete algorithms. We define polynomial and logarithmic continuous time complexity classes and show that an ODE which solves the maximum network flow problem has polynomial time complexity. We also analyze a simple flow that solves the maximum problem in logarithmic time. We conjecture that a subclass of the continuous P is equivalent to the classical P.

Our model of computation (theoretical machine) was designed for the analysis of analog Fourier optical processors, its basic data unit being a continuous image of unbounded resolution. In this paper, we demonstrate the universality of our machine by presenting a framework for arbitrary Turing machine simulation. Computational complexity benefits are also demonstrated by providing a O(log₂n) algorithm for a search problem that has a lower bound of n - 1 on a Turing machine.

A hologram can produce all the 3D depth cues that the human visual system uses to interpret and perceive real 3D objects. As such it is arguably the ultimate display technology. Computer generated holography, in which a computer calculates a hologram that is then displayed using a highly complex modulator, combines the ultimate qualities of a traditional hologram with the dynamic capabilities of a computer display producing a true 3D real image floating in space. This technology is set to emerge over the next decade, potentially revolutionizing application areas such as virtual prototyping (CAD-CAM, CAID etc.), tactical information displays, data visualization and simulation. In this paper we focus on the computational challenges of this technology. We consider different classes of computational algorithms from true computer-generated holograms (CGH) to holographic stereograms. Each has different characteristics in terms of image qualities, computational resources required, total CGH information content, and system performance. Possible trade- offs will be discussed including reducing the parallax. The software and hardware architectures used to implement the CGH algorithms have many possible forms. Different schemes, from high performance computing architectures to graphics based cluster architectures will be discussed and compared. Assessment will be made of current and future trends looking forward to a practical dynamic CGH based 3D display.

Computing practice today depends on visual output to drive almost all user interaction. Other senses, such as audition, may be totally neglected, or used tangentially, or used in highly restricted specialized ways. We have excellent audio rendering through D-A conversion, but we lack rich general facilities for modeling and manipulating sound comparable in quality and flexibility to graphics. We need coordinated research in several disciplines to improve the use of sound as an interactive information channel. Incremental and separate improvements in synthesis, analysis, speech processing, audiology, acoustics, music, etc. will not alone produce the radical progress that we seek in sonic practice. We also need to create a new central topic of study in digital audio research. The new topic will assimilate the contributions of different disciplines on a common foundation. The key central concept that we lack is sound as a general-purpose information channel. We must investigate the structure of this information channel, which is driven by the cooperative development of auditory perception and physical sound production. Particular audible encodings, such as speech and music, illuminate sonic information by example, but they are no more sufficient for a characterization than typography is sufficient for characterization of visual information. To develop this new conceptual topic of sonic information structure, we need to integrate insights from a number of different disciplines that deal with sound. In particular, we need to coordinate central and foundational studies of the representational models of sound with specific applications that illuminate the good and bad qualities of these models. Each natural or artificial process that generates informative sound, and each perceptual mechanism that derives information from sound, will teach us something about the right structure to attribute to the sound itself. The new Sound topic will combine the work of computer scientists with that of numerical mathematicians studying sonification, psychologists, linguists, bioacousticians, and musicians to illuminate the structure of sound from different angles. Each of these disciplines deals with the use of sound to carry a different sort of information, under different requirements and constraints. By combining their insights, we can learn to understand of the structure of sound in general.

The applications for Rapid Prototyping have broadened to the point where the name no longer fits the industry. The name Digital Manufacturing is proposed for the creation of solid articles from computer data without part-specific tooling and minimal geometric restrictions. The current state of the industry is reviewed and applications are classified by material strength and process accuracy. Today designers can have a 3D Printer in their office to build models and prototypes as casually as they would use an office copier. Improved materials and processes are permitting digitally manufactured articles to be used for tooling and end-use applications.

The two mainstream technologies for rewritable optical data storage are based on magneto-optical (MO) and phase-change (PC) media. In both cases a focused laser beam is used to raise the temperature of the medium beyond a certain critical temperature (i.e., melting and crystallization temperatures in the case of PC, and the Curie temperature in the case of MO) for writing, erasure, and overwriting of data. The readout of information from these media relies on the change of reflectivity of the medium (PC), or the effect of the medium on the state of polarization of the laser beam (MO). The performance of these data storage systems is characterized by the storage density of the media, achievable data rates during recording and readout, longevity, reliability, and cost of the finished products. These performance criteria in turn are determined by a host of physical and technological factors, among them: (1) Wavelength of the available semiconductor laser diodes; (2) Type of optics used in shaping the laser beam and confining it to sub-micron regions (i.e., conventional optics, near-field optics, flying lasers, integrated optics, etc.); (3) Availability of one- or two- dimensional arrays of lasers and the corresponding optics; (4) Miniature magnetic heads for thermally-assisted writing (inductive) and magneto-resistive readout; (5) Adaptive optics for beam-shaping and/or polarization control; (6) Availability of low-noise media that can deliver large readout signals; (7) Advanced signal processing techniques (both optical and electronic); (8) Multi-layer recording on stacked layers of media; (9) Novel encoding/decoding schemes for efficient use of available space on the media; (10) Mass-production of flat, rigid, low-noise patterned substrates (plastic or glass); (11) Multi-level recording. We discuss the present state of the art in optical data storage, describe the potentials and pitfalls of the existing technologies, and draw conclusions about the future of this field.

Holographic data storage allows the simultaneous search of an entire database by performing multiple optical correlations between stored data pages and a search argument. We have recently developed fuzzy encoding techniques for this fast parallel search and demonstrated a holographic data storage system that searches digital data records with high fidelity. This content-addressable retrieval is based on the ability to take the two-dimensional inner product between the search page and each stored data page. We show that this ability is lost when the correlator is defocussed to avoid material oversaturation, but can be regained by the combination of a random phase mask and beam confinement through total internal reflection. Finally, we propose an architecture in which spatially multiplexed holograms are distributed along the path of the search beam, allowing parallel search of large databases.

High memory latency is among the most critical performance factors in today's computers. To a degree it can be attributed to the high cost of fast (but low density) SRAM memory compared to slow (but high density) DRAM components. However the most important factor is the increase in access time in large memory systems caused by the communication latency. The paper describes how optical interconnections with a simple, regular topology and a modest number of optical IOs could be used to implement a memory system with a capacity of up to 1 GByte and a latency on the order of magnitude of a second level cache. The system relies on the direct integration of optical IOs on top of VLSI circuits which allows the processor to have direct, low latency, high bandwidth interconnection with hundreds of components.

Recent trends suggest that the current practice of fabricating DRAM and logic on separate dies and different processes should be reexamined. The gap between processing speed and memory latency is growing at 50% per year, and portable systems, where physical size and weight are critical issues, are becoming more popular. Merged DRAM-logic processes address these issues by combining DRAM and logic on a single die; this technology also promises to offer advantages such as increased memory bandwidth, reduced power consumption, and greater flexibility in memory organization. Merged DRAM-logic chips have already been successfully used in several commercial products. More commercial products are planned, and academic research projects are examining future uses of merged DRAM- logic processing. This paper describes the current state of merged DRAM-logic chips and examines proposed architectures, their performance and applications. Finally, tradeoffs and challenges related to the technology are discussed.

Optical interconnect is claimed to have significant advantages over electrical interconnect due to the superior physical properties of photon propagation over electron propagation. These advantages translate to the well-known fundamentally different bandwidth/distance/cross-section relationships of optical interconnects as compared to their electrical counterparts. Despite the validity of these basic results, too naive or straightforward an application of optical interconnects in electrical systems may not bring about the expected performance gains. In fact, the scientific literature contains several examples of proposed applications of optical interconnect where the real, quantifiable benefits are at best doubtful. Often, these examples are only intended to demonstrate the feasibility of a technological approach, not its great potential at the systems or application level. Typical flaws one encounters are (1) addressing the wrong problem: one tries to introduce optical interconnect at a location where the electrical interconnect is not the limiting factor; (2) failing to realize the differences between interconnect and communications; and (3) singling out one property of optical interconnect, while disregarding less beneficial properties such as latency, area, power dissipation or optical pathway cost. Capitalizing on the intrinsic potential of optical interconnects in electrical systems requires a holistic approach, that should address the real issues in future electronic systems. To assess the true benefits of replacing an electrical interconnect by an optical one, it is imperative to take the systems context in which the interconnect is to be used into account. By means of examples taken from the computing area, we shall illustrate the profound impact of this context. We then propose a possible parameter space that is intended to capture part of the relevant context information at the link level, thus providing a badly required common domain of discourse for systems designers and optical component designers.

In this paper, the role of optical interconnects in high performance computing systems is explored. A Network-of- Workstations (NOW) consists of a collection of commodity workstations or high-end Personal Computers (PCs) interconnected with a high bandwidth Local Area Network (LAN). Due to technological advances, it has been argued that NOWs can offer cost-effective high performance computing systems, ranging from low-end interactive computing to high-end parallel computing. Over the last decade the industry has been moving in this direction: Commercial high end computing systems such as the Silicon Graphics Origin 2000 multiprocessor support up to 512 dual-processor nodes interconnected with a scalable network. In this paper, we argue that when NOWs are enhanced with a new generation of very high bandwidth optical networks, they can provide supercomputer-class performance at a fraction of the cost. We describe the architectures of ring-based and star-based multi- terabit optical networks for multiprocessor systems, and discuss their impact on system performance. These networks exploit the CMOS/VCSEL optoelectronic integrated circuit technology to yield exceptionally large bandwidths with small form factors and potentially low cost. We view these new optical networks as the key to the future evolution of multiprocessor systems, and we believe that such systems can open a new era of exceptionally high performance computing.

Bandwidth incompatibility between a central processing unit (CPU) and printed circuit board (PCB) within a computer system has been a long noted problem. Physics and material sciences suggest that the problem could become worse before getting solved. This is fundamentally due to nature of propagation of electric signals in very large scale integration of conductive wires. The market has witnessed a rapid increase in chip level clock frequency (for a mainstream PC) from 100 MHz few years ago to 800 MHz nowadays. The PC bus bandwidth, however, for the same time span, grew only from 33 MHz to 100 MHz. Although the widely anticipated adoption of 133 MHz is on its way, any serious technical challenges remain. Such a large magnitude of bandwidth discrepancy between the chip and board levels has prompted Intel Corp. to aggressively invest into various technologies to increase speed at board level so that the performance of its future generation of faster and more powerful CPU chips can be effectively utilized. Rambus, Inc. with a strong backing from Intel has come up with a faster memory bus technology that can increase the bus speed several times. Competitions from sampling a data bus at both clock signal edges using the so-called double data rate (DDR) technology are also making their strides. However, high-speed electric signals in densely packed conductive wiring structures inevitably generate the so-called electromagnetic interference among each others. Tougher challenges lie ahead for future generations of large bandwidth interconnect technology at the board level.

We design and realize a scalable multi-channel free-space interconnection prototype with the potential for Tb/s.cm² aggregate bit rate capacity over inter- and intra-MCM interconnection distances. The component is prototyped in a high quality optical plastic, PMMA, using deep lithography with protons. At present data communication is achieved at 622 Mb/s per channel with a BER smaller than 10^-13 for the 16 channels with inter-channel cross-talks as low as -22dB. We perform a sensitivity analysis for misalignments and study the impact of fabrication errors on the performance of the interconnection module in case injection moulding would be the preferred mass-fabrication technique. We provide evidence that these modules can be mass-fabricated with the required precision in optical plastics suited for heterogeneous integration with semiconductor materials.

Smart photonics, the integration of optoelectronic devices with electronic circuits and systems, has growing applications in many fields, one of which is computing. An exploration of the opportunities, integration technologies, and some recent results using thin film optoelectronic and electronic device integration with Si CMOS VLSI and GaAs MESFET technologies are presented herein. Applications explored herein include low cost alignment tolerant optoelectronic interconnection links for network inerconnections, smart focal plane array processing through the integration of imaging arrays with sigma delta analog to digital converters underneath each pixel, and three dimensional computational systems using vertical through-Si optical interconnections.

As silicon CMOS circuit technology is scaled beyond the GHz range, both chipmakers and board makers face increasingly difficult challenges in implementing high speed metal interconnects. Metal traces are limited in density-speed performance due to the skin effect, electrical conductivity, and cross talk. Optical based interconnects have higher available bandwidth by virtue of the extremely high carrier frequencies of optical signals (> 100 THz). For this work, an effort has been made to determine an optimal optical tap receiver design for integration with commercial CMOS processes. Candidate waveguide tap technologies were considered in terms of optical loss, bandwidth, economy, and CMOS process compatibility. A new device, which is based on a variation of the multimode interference effect, has been found to be especially promising. BeamProp simulation results show nearly zero excess optical loss for the design, and up to 70% coupling into a 25 micrometer traveling wave CMOS photodetector device. Single-mode waveguides make the design readily compatible with wavelength multiplexing/demultiplexing elements. Polymer waveguide materials are targeted for fabrication due to planarization properties, low cost, broad index control, and poling abilities for modulation/tuning functions. Low cost, silicon CMOS based processing makes the new tap technology especially suitable for computer chip and board level interconnects, as well as metro fiber-to-the- home/desk telecommunications applications.

Successful transition from today's general-purpose programmable systems, based on the concept of planar topology, to tomorrows intelligent, highly adaptable and not necessarily programmable systems would require integration of several unorthodox approaches. We cannot predict exactly which technology will become post-CMOS and post-silicon computing mainstream. Whether it will belong to a quantum, molecular, DNA, optical, or neural paradigm, several speculations can be made to ease the transition and to create a processing infrastructure that will allow coexistence of today's semiconductor-based approach with its successor. An attempt is made here to introduce such a transitional architecture. The proposed concept of system architecture allows high- performance computing capabilities and high density free-space optical interconnects to be seamlessly integrated with power supply and cooling subsystems. This is achieved by bringing twenty hexagon-base and twelve pentagon-base pyramids into close proximity, forming truncated icosahedron. Each pyramid is an Integrated Processing-Power-supply-Cooling Module (IPPCM). IPPCM has a conical cavity within, which is occupied by a power supply/cooling unit; the optoelectronic components are attached to the faces of the pyramids. In the proposed instance, 180 trapezoidal multi-chip-processing modules, with total die-attach area equal to 2000cm², are brought into a volume of less than two liters. By bringing multiple pyramids into close proximity to each other, a free-space optical link is formed for inter-pyramidal communication. Some of the spaces formed between pyramids can be used for future unorthodox processing technologies.

Currently there is significant fundamental and practical interest in all-optical devices. For very high data rates, electro-optic or thermo-optic switching has speed limitations. Therefore all-optical switching is of considerable interest for ultrahigh data-rate computing. All-optical switching involves an intensity-dependent process. One useful configuration for optical switches is the nonlinear directional coupler. Optical switching in this device has been demonstrated for pulse widths in the picosecond region. However, these devices are relatively long which limits their practical application. By using femtosecond duration optical pulses we show that novel soliton-like coupled pulses can be used to perform all-optical switching in short nonlinear directional couplers. Because of the compact size (approximately 1 mm) and the high bit rate, a major application for these all-optical devices may be in high performance computing.

This paper proposes a novel method to construct a firewall for research network without any interruption. The advantage of the proposed method is that the construction of the firewall does never interrupt the research network which has been already running and used for everyday research activity. There are two key ideas. One is that a new protected network is created and attached on the fly to the currently used research network. The other is that migration from the old unprotected network to the new protected one is quite gradual, i.e. one computer by one computer, not all computers at once. This step by step manner ensures continuous operation of the network and interruption free firewall construction. These ideas are inspired by methods to reconstruct bridges, railroads, motorways, and so on by making bypass to avoid traffic interruption.

HAL, the disembodied robotic voice ever present in the Arthur C. Clark movie 2001, A Space Odyssey, is the archetype for artificial intelligence. What will it take to achieve HAL? Trillions of highly interconnected arithmetic units in very close proximity is mandatory. Moore's Law and 3D SILICON will get that part done. Linguistic articulation of experience and direction of action is the other missing piece. The human version's neural circuits are basically just multiply-and-add template matchers and yet verbalization of experience is the apparently automatic result. We call this recognition based logic and by embedding it in a properly interconnected processor network, the capabilities of HAL will be achieved.

The photochromic retinal protein bacteriorhodopsin (BR) is found in the cell membrane of Halobacterium salinarium. It is the key protein for photosynthetic growth of H.salinarium. BR shows an exceptional stability towards chemical, thermal, and photochemical degradation. In this paper, we propose a system of optical information storage in a BR polymer film. A three- wavelength EDRAW (Erase Direct Read After Write) experiment was performed. The photoexcited P(490) state shows a permanent storage property confirmed by our contrast ratio experiments. We have performed the reversible operations of 'write' and 'erase' with the BR polymer film over hundreds of cycles in our experiments. The readout contrast ratio is very sensitive to the intensity and wavelength of probe beam and the recorded data can be readout from 530 to approximately 630 nm with different contrast ratio. Within the range of 570 to approximately 600 nmm, the better contrast ratio can be obtained. Considering the erasing effect for the reason of absorption of P state, both higher contrast ratio and nondestructive reading can be realized by using 594 nm as the readout wavelength. The experimental result such BR material is very suitable for long-term photochromic information storage.

In order to obtain a small spot size of the data-bearing signal beam with a uniform intensity distribution at the recording plane, we studied an image folding technique using a lenslet array. The use of such a signal beam may improve the area storage density in holographic memories with a disk-shape storage medium. Computer simulations show that our technique based on image folding can give better results than the defocusing method does both in the intensity uniformity of the signal beam and in the area storage density.

It has been suggested that ultrahigh density optical storage systems could be realized by storing data in patterns with spatial coordinates below the far-field resolution limit. While the ability to write data on these fine dimensions has been shown, the ability to read data with sub-lambda resolution has proven problematic. This is especially true for memory systems that require page oriented memory access. We present a novel near-field detector array technology that is expected to satisfy the requirement of these next generation optical memory systems. Based on CMOS photoreceiver arrays and a silicon based aperture array, our device's technology is implemented using standard fabrication processes to yield a planar, near-field photoreceiver array technology. While the photoreceiver technology is an important component of our device technology, the aperture array is the fundamental component designed to enable data detection with near-field resolution. Using micro-machining technology pioneered for Micro Electro-Mechanical Systems (MEMS), fabrication of our aperture arrays depends on KOH etching of the <100> Si planes. Focused Ion Beam milling is used to realize the apertures in a thin gold film deposited on a silicon dioxide layer. We present a detailed description of both the photoreceiver circuit and the aperture array fabrication method. Independent characterization of both the photoreceiver circuit and the aperture array is also included.

The commercialization of CD ROM drives has clearly demonstrated the ability of optical storage devices to meet the growing demand for archival data storage. However, with the continued expansion of electronic information resources, storage capacity requirements are expected to approach the terabit level for personal users and exceed the petabit level for databases and data warehouse systems. Further, many data intensive applications will also require real time access data access rates. Thus, designers for the next generation of archival storage systems have the challenging task of providing storage capacities several orders of magnitude larger than existing systems while maintaining current data access times. To meet this challenge, we have been developing a 'smart' read-head device for large capacity, page-oriented optical storage systems. Further the device is designed to operate as a data filter that will pass only valid data between the optical storage system and the host computer. Based on a photonic VLSI device technology, our data filter monolithically integrates optical detectors, photoreceivers circuits, data manipulation logic, and filter control circuitry onto a single CMOS chip that can be readily fabricated using a standard VLSI fabrication facility. Thus, our device is compatible with existing electronic device manufacturing technology and shares all of the reliability, uniformity, and manufacturability benefits associated with current, electronic hardware. This paper will present an evaluation of our latest smart pixel circuits and detail our performance expectations for a 32 X 32 bit data filter chip currently under development.