This PDF file contains the front matter associated with SPIE Proceedings Volume 8680, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

An overview of electron beam tool configurations is provided. The adoption of multi-beam writing is mandatory in order to fulfill industrial needs for 11nm HP nodes and below. IMS Nanofabrication realized a 50keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1nm address grid and lithography performance capability. The new architecture will be introduced for mask writing at first, but has also the potential for 1xmask (master template) and direct wafer writing. The POC system achieves the predicted 5nm 1sigma blur across the 82μm x 82μm array of 512 x 512 (262,144) programmable 20nm beams. 24nm HP has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta) and 1st generation HVM mask writer tools in 2016. Implementing a multi-axis column configuration, 50x / 100x productivity enhancements are possible for direct 300mm / 450mm wafer writing.

PS-b-PMMA block-copolymers systems synthesized on an industrial scale, and satisfying microelectronic’s requirements for metallic contents specifications, are studied in terms of integration capabilities for lithographic applications. We demonstrate in particular that this kind of polymer can efficiently achieve periodic features close to 10 nm. These thin-films can be transferred in various substrates through dry-etching techniques. The self-assembly optimization for each polymer is first performed on free-surface, leading to interesting properties, and the changes in self-assembly rules for low molecular weight polymers are investigated and highlighted through different graphoepitaxy approaches. The enhancements in self-assembly capabilities toward low periodic polymers, as well as the broad range of achievable features sizes render PS-b-PMMA system very attractive ones for lithographic CMOS applications. We conclude showing that high-χ polymers materials developed in Arkema’s laboratories can be efficiently used to reduce the pattern’s size beyond the ones of PS-b-PMMA based BCP’s capabilities.

Overcoming the resolution-LER-sensitivity trade-off is a key challenge for the development of novel resists and processes that are able to achieve the ITRS targets for future lithography nodes. Here, we describe a process that treats lithographic patterns with aqueous solutions of block copolymers to facilitate a reduction in LER. A detailed understanding of parameters affecting adhesion and smoothing is gained by first investigating the behavior of the polymers on planar smooth and rough surfaces. Once healing was established in these model systems the methodology is tested on lithographically printed features where significant healing is observed, making this a promising technology for LER remediation.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm². In previous studies, we have focused on defects such as random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. In this work, we attempted to identify the critical imprint defect types using a mask with NAND Flash-like patterns at dimensions as small as 26nm. The two key defect types identified were line break defects induced by small particulates and airborne contaminants which result in local adhesion failure. After identification, the root cause of the defect was determined, and corrective measures were taken to either eliminate or reduce the defect source. As a result, we have been able to reduce defectivity levels by more than three orders of magnitude in only 12 months and are now achieving defectivity adders as small as 2 adders per lot of wafers.

In recent years, utilization and reduction of pattern size are following nanoimprint lithography (NIL) quickly. In nanoimprinting, since it is contact printing, a higher separation force might cause damages to the master and imprinting tool, degradation in pattern quality as well. There is a mold-release characteristic of a master and resin as one of the biggest subjects in utilization. Although Optool DSX^TM (DAIKIN Ind. Ltd.) is an de facto standard as mold releasing reagent now, there is a problem in durability at UV-NIL. Then, we focused on the material which raises the mold-release characteristic of resist. The new fluorinated copolymers based on α-chloroacrylate and the low molecular weight perfluorocompounds, added to resist was developed. In this paper, we will report these synthesis method, specific properties such as static contact angle, releasing force and further fluorinated compounds were segregated resin surface.

Directed self-assembly (DSA) of block copolymers (BCPs) is a promising technology for advanced patterning at future technology nodes, but significant hurdles remain for commercial implementation. The most widely studied material for DSA is poly(styrene-block-methyl methacrylate) (PS-PMMA), but the relatively weak segregation strength of PSPMMA results in some limitations. This paper reports on these limitations for PS-PMMA and highlights a path to success through use of more strongly segregated “high-χ” block copolymers. In general, stronger segregation is predicted to lower defectivity at equilibrium, but unfortunately, kinetics of self assembly also becomes much slower as segregation strength increases. Recognizing diffusion is much faster for cylinder morphologies than lamellar ones, we have investigated new cylinder-forming BCPs that enable defect elimination with thermal annealing processes. In addition, a formulation strategy is presented that further improves the kinetics of the assembly process, enabling tremendous improvements in defectivity over simple BCP systems. Excitingly, successful chemoepitaxy DSA with a high-χ lamellar BCP is also demonstrated using a thermal annealing process and no top coat. These technologies hold promise to enable DSA with thermal annealing processing across pitches from 40 - 16 nm.

Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed. Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be presented.

This study demonstrated our prototyped Micro Electro Mechanical System (MEMS) electron emitter which is a nc-Si (nanocrystalline silicon) ballistic electron emitter array integrated with an active-matrix driving LSI for high-speed Massively Parallel Electron Beam Direct Writing (MPEBDW) system. The MPEBDW system consists of the multi-column, and each column provides multi-beam. Each column consists of emitter array, a MEMS condenser lens array, an MEMS anode array, a stigmator, three-stage deflectors to align and to scan the multi beams, and a reduction lens as an objective lens. The emitter array generates 100x100 electron beams with binary patterns. The pattern exposed on a target is stored in one of the duplicate memories in the active matrix LSI. After the emission, each electron beam is condensed into narrow beam in parallel to the axis of electron optics of the system with the condenser lens array. The electrons of the beams are accelerated and pass through the anode array. The stigmator and deflectors make fine adjustments to the position of the beams. The reduction lens in the final stage focuses all parallel beams on the surface of the target wafer. The lens reduces the electron image to 1%-10% in size. Electron source in this system is nc-Si ballistic surface electron emitter. The characteristics of the emitter of 1:1 projection of e-beam have been demonstrated in our previous work. We developed a Crestec Surface Electron emission Lithography (CSEL) for mass production of semiconductor devices. CSEL system is 1:1 electron projection lithography using surface electron emitter. In first report, we confirmed that a test bench of CSEL resolved below 30 nm pattern over 0.2 um square area. Practical resolution of the system is limited by the chromatic aberration. We also demonstrated the CSEL system exposed deep sub-micron pattern over full-field for practical use. As an interim report of our development of MPEBDW system, we evaluated characteristics of the emitter array integrated with an active-matrix driving LSI on the CSEL system in this study. The results of its performance as an electron source for massively parallel operation are described. The CSEL as an experimental set consisted of the emitter array and a stage as a collector electrode that is parallel to the surface of the emitters. An accelerating voltage of about -5 kV was applied to the surface of the emitter array with respect to the collector. The target wafer and the emitter array were set between two magnets. The two magnets generated vertical magnetic field of 0.5 T to the surface of the target wafer. A gap between the emitter array and the target wafer was adjusted to a focus length depending on electron trajectories in the electromagnetic field in the system. The emitter array projected 100x100 electron beams with binary patterns and a dots image of its original size on the target wafer. The certain array was examined in order to evaluate the property of the e-beam exposure.

So far, the CMOS technology roadmap has been consistent with Moore’s law, even if manufacturing photolithography tools are now operating beyond their resolution limit. This has been made feasible at the expense of an intensive joint work between designers and process people who have successfully enabled double patterning processes. Tools that can provide photo lithographers with some relief are on their way although not yet in production. Among them, massively parallel mask-less electron beam lithography stands out as a serious candidate since it can achieve the required resolution at the right cost of ownership provided targeted throughput performance is reached. This paper focuses on this latter technique and more precisely, reports on simulation works performed using an emulator of the high volume manufacturing tool being developed by MAPPER Lithography, called MATRIX. In a nutshell, the MATRIX tool will operate using more than 13,000 beams, each one writing a stripe 2μm wide. Each beam itself will be composed of 49 individual sub-beams that can be blanked independently in order to write pixels onto the wafer. The residual placement errors and any current mismatch between the beams will be measured in-situ and corrected through the data path. In order to validate that this concept can actually work, the authors have built an off-line emulator of the data treatment performed down to the information sent to the blanker. It has then been plugged into an electron beam simulator such that the performance on real designs can be tested. In this paper, the methodology used for the corrections is explained as well as the validation process applied. The results of an extensive statistical study are presented showing CD, placement and residual scaling errors simulated on a set of predefined key structures assuming current and misplacement ranges within the MATRIX tool specifications, applying various correction solutions. Based on the collected data, it is shown that CD uniformity on the MATRIX tool is better than +/-10% 3σ taking into account data path, beam variation, stitching and shot noise effects, meeting specifications for circuits designed at 64nm pitch.

As design rule shrinks, it is essential that the capability to detect smaller and smaller defects should improve. There is considerable effort going on in the industry to enhance Immersion Lithography using DSA for 14 nm design node and below. While the process feasibility is demonstrated with DSA, material issues as well as process control requirements are not fully characterized. The chemical epitaxy process is currently the most-preferred process option for frequency multiplication and it involves new materials at extremely small thickness. The image contrast of the lamellar Line/Space pattern at such small layer thickness is a new challenge for optical inspection tools. In this investigation, the focus is on the capability for optical inspection systems to capture DSA unique defects such as dislocations and disclination clusters over the system and wafer noise. The study is also extended to investigate wafer level data at multiple process steps and determining contribution from each process step and materials using ‘Defect Source Analysis’ methodology. The added defect pareto and spatial distributions of added defects at each process step are discussed.

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10 wafers per hour. By clustering several of these systems together high throughputs can be realized in a small footprint. This enables a highly cost-competitive solution for either direct patterning or complementary patterning approach, [1, 2]. For a 10 wph throughput per unit MAPPER will use 13,260 parallel electron beams, delivering 170 μA to the wafer. To realize this large current at the wafer MAPPER uses its patterned beam approach where each beam consists of 49 subbeams [3]. MAPPER is currently realizing its MATRIX platform. This system is one unit in the cluster depicted above and will have a capability of 10 wph (containing the patterned beams approach) and have full overlay capability. One 10 wph unit will have a footprint of 1.1 m x 1.65m. This paper will provide an overview of the development status of this MATRIX platform.

The Vistec VB300 Gaussian electron-beam lithography system at the College of Nanoscale Science and Engineering (CNSE) in Albany routinely exposes 300 mm wafers to meet the requirements of nano-patterning for metrology and process tool qualification. CNSE and Vistec are partners in a continuous throughput improvement program. The first stage of this program has recently been implemented on CNSE’s VB300. To quantify the improvements, we have defined a suite of benchmark patterns to compare throughput “before and after”, which we plan to use throughout the entire program. These benchmark patterns show throughput improvements of up to a factor of 2.5 on the VB300. We believe this method of measuring throughput could be applied to other lithography systems that exhibit a throughput dependency on pattern type.

The data delivery throughput of electron beam lithography systems can be improved by applying lossless image compression to the layout image and using an electron beam writer that can decode the compressed image on-the-fly. In earlier research we introduced the lossless layout image compression algorithm Corner2, which assumes a somewhat idealized writing strategy, namely row-by-row with a raster order. The MAPPER system has electron beam writers positioned in a lattice formation and each electron beam writer writes a designated block in a zig-zag order. We introduce Corner2-MEB, which redesigns Corner2 for MAPPER systems.

The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area roll to roll (R2R) manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we have developed a roll based J-FIL process and applied it to technology demonstrator tool, the LithoFlex 100, to fabricate large area flexible bilayer wire grid polarizers (WGP) and high performance WGPs on rigid glass substrates. Extinction ratios of better than 10000 were obtained for the glass-based WGPs. Two simulation packages were also employed to understand the effects of pitch, aluminum thickness and pattern defectivity on the optical performance of the WGP devices. It was determined that the WGPs can be influenced by both clear and opaque defects in the gratings, however the defect densities are relaxed relative to the requirements of a high density semiconductor device.

Pattern customization is a necessary requirement to achieve circuit-relevant patterns using block copolymer directed self-assembly (DSA), but the edge-placement error associated with customization steps after DSA is anticipated to be at the scale of the pattern features, particularly as a result of overlay error. Here we present a new self-aligned approach to the customization of line-space patterns fabricated through chemical epitaxy. A partially inorganic chemical pattern contains a prepattern with pinning lines and non-guiding “blockout” features to which the block copolymer domains are aligned. Pattern transfer results in a line-space pattern with self-aligned customizations directly determined by the prepattern. In the transferred pattern, pinning lines determine the placement of single-line gaps while blockout features determine the placement and size of perpendicular trim across lines. By using designed two-dimensional chemical patterns, this self-aligned, bidirectional customization scheme enables the fabrication of high-resolution circuit-relevant patterns with fewer trim/exposure steps.

Predicting directed self-assembly (DSA) patterns from given chemoepitaxy or graphoepitaxy directing patterns is a well known direct problem of computational DSA simulations. This paper concentrates on inverse problem of DSA – finding directing graphoepitaxy or chemoepitaxy patterns, resulting in given desired DSA patterns. Approaches to computational solution of inverse DSA problem are discussed, particularly the ones based on a linearization of the DSA model and minimizing the objective function ensuring the formation of the desired DSA patterns. We illustrate these approaches by presenting the results of their application to an inverse DSA problem for contact holes patterned using graphoepitaxy guiding templates.

Block copolymer (BCP) directed self-assembly (DSA) is a promising extension of optical lithography for patterning irregularly positioned contact holes of integrated circuits. The small topographical templates are shown to guide the self-assembly off the natural geometry by strong boundary confinement [1-2], and has been demonstrated to pattern 22nm random logic circuits using [2-3]. Here we present a general template design strategy that relates the DSA material properties to the target technology node requirements and experimentally demonstrated DSA contact hole patterning for half adders at the 14 nm and 10 nm nodes.

Directed self-assembly (DSA) process of block copolymers (BCPs) has been considered as a candidate for sub-20nm contact patterning. In recent years the semiconductor manufacturers have been interested in use DSA in production. DSA is based on the intrinsic property of the BCPs which is phase-separation in the molecular scale, but significant problems remain for device application. Process time, high process temperature, defect, and CD distribution make the using of DSA difficult in mass production. One of the most considered problems for DSA is the CD Distribution. A guide material for grapho-epitaxy DSA process requires resistance against high temperature and solvent. We use negative tone develop (NTD) photoresist (PR) guide for simple process and thermal resistance, and additional treatment for resistance against high temperature and solvent. The CD distribution of DSA is highly related to the phase separation itself. In order to get better performance, the polymer chains should have sufficient mobility under heating above their glass temperature. Therefore, film thickness and molecular weight of BCPs are very important parameters for CD distribution of DSA process. From the results, it is proven that guide materials, film thickness of BCPs, and molecular weight of BCPs are significant parameter in order to improve CD distribution of DSA patterns.

The goal of this paper is to investigate the potential of Directed Self-Assembly (DSA) to address contact via level patterning, by either Critical Dimension (CD) shrink or contact multiplication. Using the 300mm pilot line available in LETI and Arkema materials, our approach is based on the graphoepitaxy of PS-b- PMMA block copolymers (BCP). The process consists in the following steps: a) the lithography of guiding patterns, b) the DSA of block copolymers and PMMA removal and finally c) the transfer of PS patterns into the under-layer by plasma etching. Several integration schemes using 193nm dry lithography are evaluated: negative tone development (NTD) resists, a tri-layer approach, frozen resists, etc. The advantages and limitations of each approach are reported. Furthermore, the impact of the BCP on the final patterns characteristics is investigated by tuning different parameters such as the molecular weight of the polymeric constituents and the interaction with the substrate. The optimization of the self-assembly process parameters in terms of film thickness or bake (temperature and time) is also reported. Finally, the transfer capabilities of the PS nanostructures in bulk silicon substrate by using plasma-etching are detailed. These results show that DSA has a high potential to be integrated directly into the conventional CMOS lithography process in order to achieve high-resolution contact holes. Furthermore, in order to prevent design restrictions, this approach may be extended to more complex structures with multiple contacts and nonhexagonal symmetries.

Properly designed geometries of directing pre-patterns broaden the set of lattice symmetries and the local arrangements of patterns achievable by directed self-assembly (DSA) of block copolymers (BCP), compared to the ones achievable in un-directed, bulk systems. We present the results of parametric computational simulation studies, concentrating on exploring the chemoepitaxy or graphoepitaxy directing geometries yielding the DSA structures needed for typical integrated circuits, but not achievable in bulk, undirected annealing of BCP. The examples include the parametric studies of chemoepitaxy and graphoepitaxy DSA patterns etch-transferrable, respectively, into isolated lines and contact hole arrays. The results of the DSA defect simulations are also presented and discussed.

We use self-consistent field theory (SCFT) to study the self-assembly of cylinder-forming diblock copolymers confined in a cylindrical prepattern. This situation arises in contact holes -the hole shrink problem- where the goal is to produce a cylindrical hole with reduced dimensions relative to a guiding prepattern. In this study, we focus on systems with a critical dimension (CD) ranging from 50nm to 100nm and which consequently lead to the formation of a single cylinder in the middle of the hole. We found that different morphologies arise from the self-assembly process and are strongly governed by the prepattern dimensions, wetting conditions as well as the polymer molecular weight. We also considered blends of diblock copolymers and homopolymers and determined optimal blending configurations that not only favor the formation of the desired cylindrical morphology but also extend the processing window relative to the pure diblock case.

Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full advantage of DSAL requires diminishing not only systematic error modes but also random error modes by carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only systematic errors but also random errors qualitatively by simulations.

We use self-consistent field theory (SCFT) to study the directed self-assembly of cylinder-forming diblock copolymers laterally confined in narrow channels. The side walls and top/bottom surfaces of the channel are either all major block attractive, all minor block attractive, or a combination of major block attractive on the top surface and minor block attractive on the remaining film surfaces. We focus on systems in which the self-assembled cylinders form a monolayer oriented parallel to the sidewalls in a thin channel. Experimentally and theoretically, well-ordered perfect cylinders are observed in narrow channels, but undesirable defective structures are also found. We investigate the energetics of isolated, meta-stable defects and compare them with two types of defects (dislocations and disclinations) recently investigated in laterally confined lamellar block copolymer systems using SCFT. Our simulation results are also compared with defect energy estimates for lying down cylinder monolayers extracted from experimental work by Mishra and coworkers. Parametric studies include the effects of film thickness, domain spacing, χN, and composition on defect energies with various wall wetting conditions in narrow channels of varying widths. A major finding is that defects of cylindrical directed self-assembly in a confined channel have a smaller free energy cost (tens of kT) in comparison with defects in laterally confined, vertically oriented lamellae (many tens of kT). We also discovered a novel vertically branched cylinder defect in the case of neutral top and bottom surfaces with significantly lower defect energy than a corresponding dislocation defect. More broadly, this study reveals unexpected dependences of equilibrium defect densities on a wide range of parameters that must be carefully controlled in order to successfully implement a directed self-assembly process with block-copolymers.

As present CMOS devices approach technological and physical limits at the sub-10 nm scale, a ‘beyond CMOS’ information-processing technology is necessary for timescales beyond the semiconductor technology roadmap. This requires new approaches to logic and memory devices, and to associated lithographic processes. At the sub-5 nm scale, a technology platform based on a combination of high-resolution scanning probe lithography (SPL) and nano-imprint lithography (NIL) is regarded as a promising candidate for both resolution and high throughput production. The practical application of quantum-effect devices, such as room temperature single-electron and quantum-dot devices, then becomes feasible. This paper considers lithographic and device approaches to such a ‘single nanometer manufacturing’ technology. We consider the application of scanning probes, capable of imaging, probing of material properties and lithography at the single nanometer scale. Modified scanning probes are used to pattern molecular glass based resist materials, where the small particle size (<1 nm) and mono-disperse nature leads to more uniform and smaller lithographic pixel size. We also review the current status of single-electron and quantum dot devices capable of room-temperature operation, and discuss the requirements for these devices with regards to practical application.

High Performance Single Nanometer Lithography (SNL) is an enabling technology for beyond CMOS and future nanoelectronics. To keep on with scaling down nanoelectronic components, novel instrumentation for nanometer precise placement, overlay alignment and measurement are an essential pre-requirement to realize Next Generation Lithography (NGL) systems. In particular, scanning probe based methods for surface modification and lithography are an emerging method for producing sub-10 nm features. In this study, we demonstrate nano-scale lithography using a scanning probe based method in combination with a Nanopositioning and Nanomeasuring Machine. The latter one has a measuring range of 25 mm x 25 mm x 5 mm, 0.1 nanometer resolution and outstanding nanometer accuracy. The basic concept consists of a special arrangement allowing Abbe error free measurements in all axes over the total scan range. Furthermore, the Nanopositioning and Nanomeasuring Machine is able to store the exact location that can be found again with an accuracy of less than 2.5 nanometers. This system is also predestinated for critical dimension, quality and overlay control. The integrated scanning probe lithography is based on electric-field-induced patterning of calixarene. As a result, repeated step response tests are presented in this paper.

The prosperous demonstration of a technique able to produce features with single nanometer (SN) resolution could guide the semiconductor industry into the desired beyond CMOS era. In the lithographic community immense efforts are being made to develop extreme ultra-violet lithography (EUVL) and multiple-e-beam direct-write systems as possible successor for next generation lithography (NGL). However, patterning below 20 nm resolution and sub-10 nm overlay alignment accuracy becomes an extremely challenging quest. Herein, the combination of electron beam lithography (EBL) or EUVL with the outstanding capabilities of closed-loop scanning proximal probe nanolithography (SPL) reveals a promising way to improve both patterning resolution and reproducibility in combination with excellent overlay and placement accuracy. In particular, the imaging and lithographic resolution capabilities provided by scanning probe microscopy (SPM) methods touches the atomic level, which expresses the theoretical limit of constructing nanoelectronic devices. Furthermore, the symbiosis between EBL (EUVL) and SPL expands the process window of EBL (EUVL) far beyond state-of-the-art allowing SPL-based pre- and post-patterning of EBL (EUVL) written features at critical dimension level with theoretically nanometer precise pattern overlay alignment. Moreover, we can modify the EBL (EUVL) pattern before as well as after the development step. In this paper we demonstrate proof of concept using the ultra-high resolution molecular glass resist calixarene. Therefor we applied Gaussian E-beam lithography system operating at 10 keV and a home-developed SPL set-up. The introduced Mix and Match lithography strategy enables a powerful use of our SPL set-up especially as post-patterning tool for inspection and repair functions below the sub-10 nm critical dimension level.

While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct patterning is still being considered as an alternative or complementary approach for patterning of advanced technology nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore, degradation of product reliability may occur. These questions have not yet been clarified in detail. For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits, suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes.

As the feature size of LSI shrinks, the cost of mask manufacturing and turn-around-time continue to increase. Maskless lithography using electron beam direct writing (EBDW) technology attracts attention. On the other hands, with continuous scaling and the introduction of low-k dielectrics in Cu interconnect technology, time-dependent dielectric breakdown (TDDB) reliability has become one of important issues. Therefore, EBDW in backend process is needed to ensure superior patterning quality and TDDB reliability using high-accuracy proximity effect correction. In this paper, we propose an EBDW strategy for throughput enhancement considering reliability for TDDB degradation of LSI interconnects. Patterns with short and long TDDB degradation lifetime are drawn by fine and coarse dose adjustments, respectively. We applied the proposed method to a microprocessor layout synthesized with the Nangate 45nm Open Cell Library. As a result, the drawn pattern with coarse dose adjustment achieved 12.5% higher throughput than that of fine dose adjustment. The drawing error increased by only 6.5%.

Multiple e-beam direct write lithography (MEBDW), using >10,000 e-beams writing in parallel, proposed by MAPPER, KLA-Tencor, and IMS is a potential solution for 20-nm half-pitch and beyond. The raster scan in MEBDW makes bitmap its data format. Data handling becomes indispensable since bitmap needs a huge data volume due to the fine pixel size to keep the CD accuracy after e-beam proximity correction (EPC). In fact, in 10,000-beam MEBDW, for a 10 WPH tool of 1-nm pixel size and 1-bit gray level, the aggregated data transmission rate would be up to 1963 Tera bits per second (bps), requiring 19,630 fibers transmitting 10 Gbps in each fiber. The data rate per beam would be <20 Gbps. Hence data reduction using bigger pixel size, fewer grey levels to achieve sub-nm EPC accuracy, and data truncation have been extensively studied. In this paper, process window assessment through Exposure-Defocus (E-D) Forest to quantitatively characterize the data truncation before and after EPC is reported. REBL electron optics, electron scattering in resist, and resist acid diffusion are considered, to construct the E-D Forest and to analyze the imaging performance of the most representative layers and patterns, such as critical line/space and hole layers with minimum pitch, cutting layers, and implant layers, for the 10-nm, and 7-nm nodes.

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3σ std) of alignment mark readings can be achieved while being robust against various process steps.

Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning step, and such results provide a foundation for our ongoing efforts to integrate the DSA patterning step into a robust process for fabricating device layers. Here we provide a status report on the integration of two chemoepitaxy DSA patterning methods for the fabrication of 28nm pitch Si fin arrays. In addition to the requirements for a robust pattern transfer process, it is also important to understand the pattern design limitations that are associated with DSA. We discuss some of the challenges and opportunities associated with developing efficient device designs that take advantage of the capabilities of DSA.

The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy guiding pattern was created by the IBM Almaden approach using brush materials in combination with an optional chemical slimming of the resist lines. Critical dimension (CD) uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of the DSA process were characterized. CD rectification and LWR reduction were observed. The chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly improving the DSA PW under over-dose conditions. However, the overall PW was found to be smaller than without using the slimming, due to a new failure mode at under-dose region.

Directed Self Assembly (DSA) using block copolymers (BCP) has received considerable attention over the past few years as a potential complementary lithographic technique. While many are focused on adapting DSA integrations to high volume manufacturing, the key to the technology’s success lies in its ability to generate low defect patterns. The best way to drive the technology toward a zero defect solution is to understand the fundamentals of the block copolymer assembly, the interactions of the block copolymer with the underlying chemical pattern, and the evaluation of process parameters to obtain a high degree of order of the BCP morphologies. To this end, recent research has investigated numerous material, structural, and process sensitivities of an exemplary chemo-epitaxy line/space integration. Using the DSA flow implemented at imec, substrate properties, such as the geometry and chemistry, were studied and provided the first results regarding the dimensions of the nano-patterns and the energetic conditions necessary to obtain good alignment of the BCP. Additional parameters that have been explored include BCP film thickness and the bake conditions used to execute various steps of the flow. With this work, the key parameters that drive the assembly process have been identified. This will allow the definition of an optimized process window and materials for defect minimization.

Morphological defects of block copolymers are dynamically formed during the annealing step of directed self­ assembly (DSA) process. Understanding the dynamics of such defects is crucial to manufacture defect-free wafers, however it is not well-understood due to difficulties in in-situ measurements. In order to provide some insights into this problem, we have performed dynamic simulations of symmetric diblock copolymers on chemically pre-patterned surface. A simplified model, so-called the Ohta-Kawasaki (OK) model was employed in this study, whose free energy and chemical potential were expressed as a function of the local order parameters. Time evolution of the local order parameters were calculated numerically and iteratively from the equation of continuity. As a test case, the two-dimensional (2D) dynamic simulations were performed including thermal fluctuations. The time evolution of the lamella defects was successfully characterized as a function of the interactive strength between the diblock copolymers and the chemically pre-patterned surface. In the three­ dimensional (3D) dynamic simulations, some complicated morphologies formed on the chemically pre-patterned surface were found to be similar to those obtained from Monte Carlo simulations. Our preliminary simulation data prove that for small _χNs, dynamic simulations of diblock copolymers with OK model could be a powerful method to predict DSA defects with reasonable accuracy and with small computational cost.

We report morphology of cylinder of diblock copolymers (BCP), which consist of polymer A and B, in cylindrical prepattern holes by dissipative particle dynamics simulation in order to predict optimal cylinder profile. Configuration of cylinder which consists of polymer B changes along with change of affinity of underlayer and guide wall for BCP. In the case of underlayer, neutral to both the polymer species shows the most stable cylinder shape. When affinity converts to either polymer, cylinder shape gets distorted. In the case of intergrading guide wall condition from A wet to B wet for a certain hole CD, polymer B, that constitutes cylinder, gradually loosen and stack on the guide eventually. Moreover cylinder forms again for B wet larger hole. Free energy for hole CD is also investigated and the profile shows A wet wall and B wet wall are suitable for hole shrink in a narrow and wide range of hole CD, respectively. Because free energy of A wet wall varies widely for hole CD change. In contrast, free energy of B wet wall exhibits no significant changes and the profiles signify that cylinder shapes relatively stable in wider range than A wet wall.

Dissipative particle dynamics (DPD) simulations are utilized to optimize contact hole shrink process using graphoepitaxial directed self-assembly (DSA). In this work, poly (styrene-block-methyl methacrylate) (PS-b-PMMA) was employed. In the contact hole shrink process, PS residual layer was formed on the bottom floor of the hole type prepattern. To realize reliable contact hole shrink process, minimization of the thickness of PS residual layer was one of the key issues. It was found that the minimization of the thickness of the PS residual layer and optimization of threedimensional configuration of the PMMA domain was trade-off relationship. By using DPD simulations, the parameters were successfully optimized to achieve residual layer free contact hole shrink of DSA lithography.

Directed self-assembly (DSA) of block copolymers (BCP) has attracted significant interest due to its promising potential as the next generation lithography candidate. In this paper we used Self-Consistent-Field-Theory (SCFT) to computationally simulate the equilibrium behavior of self-assembly inside a confinement well, which is also known as graphoepitaxy. More specifically, we studied the DSA of cylinder-forming block copolymers for contact hole/via patterning, mainly focusing on 1-hole DSA pattern inside confinement well. The SCFT simulation results of parametric studies for confinement well sizes ranging from 50nm to 90nm, different polymer film thicknesses and a range of the wall/substrate affinity parameter values, are presented, as well as verified by experiments.

The advantage of blend DSA (Directed Self Assembly) is milder anneal condition than PS-b-PMMA BCP DSA materials and availability of conventional instruments. In this paper, blend type DSA was applied for hole patterning. Target patterns were contact hole and oval hole. Polymer phase separation behavior has been studied from the point of χN. In the case of polymer blend, χN needs to be more than 2 to give phase separation. At first the effect of polymer size was studied. When the polymer weight was low, the shrunk hole was not clean because of low χN. Furthermore, the correlation of shrink amount and χN was studied. Higher χN polymer blend system gave higher shrink amount. High χN polymer systems give clear interface, then the intermixing area would be reduced, then the attached polymer blend part became larger. The polymer blend ratio effect was also investigated. The blend ratio was varied for polymer A/ polymer B=70/30-50/50. The shrink amount of oval hole was reduced with increasing the ratio of polymer B. However, the shrink amount ratio of CDY/CDX was almost constant (~3).

Micro-phase separation for directed self-assembly (DSA) can be executed successfully only when the substrate surface on which the block co-polymer (BCP) is coated has properties that are ideal for attraction to each polymer type. The neutral underlayer (NUL) is an essential and critical component in DSA feasibility. Properties conducive for BCP patterning are primarily dependent on “brush” or “crosslinked” random co-polymer underlayers. Most DSA flows also require a lithography step (reflection control) and pattern transfer schemes at the end of the patterning process. A novel multifunctional hardmask neutral layer (HM NL) was developed to provide reflection control, surface energy matching, and pattern transfer capabilities in a grapho-epitaxy DSA process flow. It was found that the ideal surface energy for the HM NL is in the range of 38-45 dyn/cm. The robustness of the HM NL against exposure to process solvents and developers was identified. Process characteristics of the BCP (thickness, bake time and temperature) on the HM NL were defined. Using the HM NL instead of three distinct layers – bottom anti-reflective coating (BARC) and neutral and hardmask layers – in DSA line-space pitch tripling and contact hole shrinking processes was demonstrated. Finally, the capability of the HM NL to transfer a pattern into a 100-nm spin-on carbon (SOC) layer was shown.

We have prepared and analyzed neutralization layer material to perform perpendicular morphology of Poly (styrene-block-methyl methacrylate) (PS-b-PMMA) as Block-Co-Polymers (BCPs). Neutralization layer surface property is optimized by changing hydrophilicity. We have evaluated two types of neutralization layer material. First one is graft type polymer which makes chemical bonding to substrate. The other is crosslink type polymer which becomes insoluble to organic solvent by thermal crosslink reaction. We checked neutralization function by changing film thickness of the neutralization layer under PS-b-PMMA. Regarding to graft type, it was found that when the film thickness of neutralization layer is over 2.3 nm, PS-b-PMMA forms perpendicular morphology on appropriate neutralization layer. Similarly, regarding to crosslink type, it was found that when the film thickness of neutralization layer is over 1.9 nm, PS-b-PMMA forms perpendicular morphology on appropriate neutralization layer. Finally, we will show lamella and cylinder patterns changing L₀ of PS-b-PMMA on neutralization layer.

Using the Leibler-Ohta-Kawasaki (LOK) phase-field model of block copolymers (BCPs), we characterize how a chemoepitaxial template with parallel lines of arbitrary width affects the BCP microdomain shape. We apply boundary conditions that account for the interactions of the polymers with the templated substrate and a neutral top-coat. We derive formulas for the monomer density and the microdomain interface profile of periodic, lamellar BCP melts whose template lines are wider or narrower than the bulk microdomain width. For such systems, our analysis (i) shows that mass conservation causes the microdomain interfaces to oscillate about their bulk positions and (ii) determines the length scale λ over which these oscillations decay away from the substrate.

As directed self-assembly (DSA) has gained momentum over the past few years, questions about its application to high volume manufacturing have arisen. One of the major concerns is about the fundamental limits of defectivity that can be attained with the technology. If DSA applications demonstrate defectivity that rivals of traditional lithographic technologies, the pathway to the cost benefits of the technology creates a very compelling case for its large scale implementation. To address this critical question, our team at IMEC has established a process monitor flow to track the defectivity behaviors of an exemplary chemo-epitaxy application for printing line/space patterns. Through establishing this baseline, we have been able to understand both traditional lithographic defect sources in new materials as well as new classes of assembly defects associated with DSA technology. Moreover, we have explored new materials and processing to lower the level of the defectivity baseline. The robustness of the material sets and process is investigated as well. In this paper, we will report the understandings learned from the IMEC DSA process monitor flow.

Bit-patterned media (BPM) is a candidate for high-density magnetic recording media. Directed self-assembly (DSA) is expected to be a solution for the fabrication process of high-density BPM. A BPM with 20 nm-pitch dot pattern is fabricated. A 100 nm-pitch triangle lattice dot pattern, which is fabricated by EB lithography, is used as a guide post to order PS-PDMS self-assembled diblock co-polymer with 20 nm pitch. Dot-pitch fluctuation and linearity of pseudo dot tracks are estimated. The standard deviation of the dot-pitch variation including the post guide is 8% of the self-assembled dot pitch. The dot-position deviation is estimated to be about 8% of the pseudo dot track pitch. In both cases, variation of the size and pitch of the post guides is found to increase the dot-pitch fluctuation and dot-position deviation from pseudo dot-track.

Poly(styrene)-b-poly(acrylic acid) copolymers (PS-b-PAA) was shown to be one promising material for achieving substantially smaller pitch patterns than PS-b-PMMA while still retaining high etch contrast and application for chemoepitaxy. Phase separation of acetone vapor annealed PS-b-PAA (Mw=16,000 g/mol with 50:50 volume ratio of PS: PAA) on PS brush achieved a lamellar morphology with a pattern pitch size (L₀) of 30 nm. However the thermal annealing of the same PS-b-PAA generated a dramatically larger pitch size of 43 nm. SEM and GPC analysis revealed that the intermolecular crosslinking during thermal annealing process has increased the effective N (degree of polymerization), which suggests that even a small amount of crosslinking would lead to big pitch change. Thus, PS-b-PAA is not suitable for fast thermal annealing process as it loses pitch size control due to PAA crosslinking.

As an alternative lithography technique, directed self-assembly (DSA) of block copolymers has shown to be promising for next generation high resolution patterning. PS-b-PMMA has been widely studied for its use as a block copolymer in directed self-assembly and has demonstrated patterned features down to size scales on the order of 20 nm pitch. However, due to the modest χ value for PS-b-PMMA (χ=0.038), this 20 nm feature pitch representes roughly the limiting capability of PS-b-PMMA. To achieve smaller pitch features, new block copolymers with higher χ values must be developed for use in DSA lithography. Here, poly(styrene)-b-poly(hydroxyehtylmethacrylate) or PS-b-PHEMS is introduced as one possible such high χ polymer. PS-b-PHEMA with controlled Mw and PDI was successfully synthesized via ATRP and fully characterized by NMR, GPC and FTIR. As a first demonstration of sub-20 nm pitch capability in PS-b-PHEMA, a 15 nm pitch size lamella structure in PS-b-PHEMA is shown. PS-b-PHEMA has good thermal stability, allowing it to be rapidly annealed thermally. PS-b-PHEMA also is shown to have improved etch contrast between the two blocks as compared to PS-b-PMMA. The χ value for PS-b-PHEMA is estimated to be 0.37 based on experimental pitch scaling studies, which is almost 10 times of the χ value for PS-b-PMMA.

Directed self-assembly (DSA) of block copolymers (BCP) could enable high resolution patterning beyond the capabilities of current optical lithography methods via pitch multiplication from lower resolution primary lithographic patterns. For example, DSA could enable dense feature production with pitches less than 80 nm from patterns generated using 193 nm exposure tools without the need for double patterning or other schemes. According to theory, microphase separation of diblock copolymers occurs when the critical condition that χN>10.5 is met while the pitch of the resulting polymer features scale as ~N^2/3, where χ is the Flory Huggins interaction parameter and N is the total degree of polymerization for the diblock copolymer. In order to generate patterns with smaller pitches, N must be decreased while maintaining a χN>10.5 to allow for phase separation. This requires utilization of polymers with higher χ values as N is decreased. Current materials, such as PS-b-PMMA, exhibit a relatively low χ value of ~0.04, which limits the practical pitch of DSA line-space patterns produced using PS-b-PMMA to approximately 20 nm. In this paper, we investigate alternative materials, namely poly(styrene)-b-poly(hydroxystyrene) (PS-b-PHOST), which exhibits a high χ value via hydrogen bonding interactions that can allow for production of sub-20nm pitch DSA patterns. In order to utilize any diblock copolymer for DSA, a neutral underlayer and a method for annealing the block copolymer are required. Here, a random copolymer, poly(styrene-co-hydroxystyrene-co-glycidyl methacrylate), is developed and reported for use as a neutral underlayer for PS-b-PHOST. Furthermore, a solvent annealing method for PS-b-PHOST is developed and optimized using ethyl acetate to allow for uniform microphase separation of PS-b-PHOST.

A model has been developed for the simulation of block copolymer (BCP) directed self-assembly (DSA) based on a coarse grained polymer model that anneals using molecular dynamics. The model uses graphics processing units (GPUs) to perform the calculations; this combined with the coarse graining means simulations times approach the speed of other more commonly used simulation techniques for BCPs. The model is unique in how it treats the pure phase blocks interactions with themselves (i.e. A-A and B-B interactions) and their interactions with each other. This allows for simulations that can potentially more accurately capture the differences between the properties of each block such as density and cohesive energy. The model is fully described and used to examine some of the issues that are unique to DSA lithographic applications of BCPs. We describe a method to calculate χ for the off-lattice MD system based on observation of the order-disorder transitions (ODT) for different degrees of polymerization N. The model is used to examine the transient, complex, non-classical morphologies that can occur through film thickness during a DSA process. During the phase separation process from a mixed initial state, the BCPs first locally phase separate to form small aggregate type structures. These aggregates then coalesce into larger features that approach the size of the equilibrium domain. These features then shift to match the guiding pattern on the underlayer followed by the slow elimination of defects. We also studied how the guiding patterns work in chemo-epitaxy DSA. The guiding patterns have a strong immediate effect on the BCP film nearest the interface and induce locally aligned self-assembly. Over time, this induced pattern tends to propagate up through the thickness of the film until the film is uniformly aligned to the guiding pattern. We also clearly see that the observed morphology at the top of the film gives no indication of the morphology through the depth, especially during the transient portions of the self-assembly process.

A 10% batch-to-batch variation in molecular weight for a low polydispersity block copolymer (BCP) used for DSA lithography could result in more than a 6% change in critical dimension (CD). Therefore, there is a strong motivation and need to develop and understand methods for fine-tuning the domain size of DSA BCPs to meet the CD and pitch specifications that will be required for practical implementation of DSA processes. This study investigates two methods of fine-tuning the domain size of a specific batch of BCP through blending of the BCP with another polymer, either 1. a set of similar homopolymers (HPs) or 2. a similar BCP of different molecular weight. Each method was investigated and compared using a coarse grained molecular dynamics simulation. For BCP-HP blends, the domain size increases as the amount of HP increases because the HPs tend to slightly swell the BCP domains. A design heuristic was developed for guiding the determination of how much HP to add to obtain a desired pitch. For blends of different molecular weight BCPs, two different scaling regimes were identified; one regime is majority large chains and the other regime is majority small chains. Based on the simulation results, the domain scaling can be mapped across the full range of blends by simply measuring three points: the pure small chain domain size, the pure large chain domain size, and a 50/50 blend of the small and large chains. Comparing the two different blending methodologies, BCP blending with other BCPs is a more versatile approach because it can be used to either increase or decrease the domain size of a base BCP while HP blending can only increase the domain size. HP blending is also potentially problematic because the HPs tends to aggregate in the middle of each block’s half domain which can have a significant effect on CD uniformity due to the strong effect of local variations in the concentration of the HP and local variations in HP conformation. The use of BCP blends with other BCPs should be more favorable from a CD uniformity perspective because this approach is much less susceptible to initial local fluctuations than HP blends because all BCPs go to the A-B interface. The coarse grained molecular dynamics simulation is well suited for comparisons such as this and can produce design rules that are needed for experimental implementation of polymer blending with BCPs to tune domain size.

This paper addresses two fundamental issues: (1) the connection between block copolymer polydispersity (as measured by a polydisperisty index (PDI)) and pattern LER/ LWR limits and (2) the connection between block copolymer χN value and pattern LER/LWR limits. In this work, we have used coarse grained molecular dynamics (MD) simulations of BCP DSA to study the effect of block copolymer PDI on DSA properties including LER/LWR and patterning capability. It is observed that as PDI increases from 1 to values of ~1.3, there is little effect on pattern LER/LWR, and as PDI increases above ~1.3 the LER/LWR increases slowly with increasing PDI. This suggests that LER/LWR concerns are not a major determinant in terms of specifying block copolymer PDI requirements for DSA processes. Concerning χN and LER/LWR, there is a sharp increase in roughness for χN<30. Because of the sharp increase at such low χN values, it is unlikely that BCP DSA processes for semiconductor manufacturing will be able to operate at low χN values even though microphase separation still occurs at these low χN values.

Although maskless electron beam lithography is viewed as an alternative lithographic technology by the mainstream semiconductor industry, it has long been a key lithographic tool of the compound semiconductor devices. It combines very high resolution with a high depth of field, but its wide acceptance in semiconductor production has been hindered by lower throughput when compared to optical lithography. Several new approaches to parallel e-beam lithography are currently being developed. These technologies, however, have not yet demonstrated the throughput per dollar invested that the current optical tools achieve. Given the cost and high throughput requirements set by most semiconductor manufacturers, the new parallel e-beam lithography tools are likely to be used for processing only a few critical layers, similar to the way the older electron beam tools are used by compound semiconductor manufacturers. Overlay accuracy is another big challenge when mixing optical and E-beam lithography tools. An alignment mark strategy is needed which will results in optimum registration accuracy between E-beam and optically defined layers on the chip.

We present a method to direct the self-assembly of PS/PMMA block co-polymer by surface chemical modification using atomic force microscopy (AFM) based nanolithography. In our approach, a PS-OH brush layer is chemically modified by the AFM tip, creating a nanometer scale guiding pattern that induces the alignment of the block co-polymer. Compared to alternative procedures that involves electron beam or deep UV lithography, AFM nanolithography is a simpler process since it does not require the use of an additional resist processing step. In addition, AFM nanolithography presents the potential to define the guiding patterns with better control and resolution.

Image contrast of line-cut and contact hole features patterned using Complementary E-Beam Lithography (CEBL) at advanced technology nodes are analyzed. The study assumes one beam in each column is used to pattern features less than 20 nm (Full Width Half Maximum, FWHM), consistent with Multibeam’s multi-column vector-scan approach for CEBL patterning. When the feature size approaches the resolution of the e-beam column design, the dose intensity profile follows a Gaussian model. Using Gaussian profiles, the image contrast of line cut or contact hole features can be studied as a function of beam FWHM size, spacing between features, and proximity effect. As expected, the image contrast was dominated by contact hole stepping distance (i.e., spacing between neighboring contact holes) and proximity effect. The plot of image contrast versus contact position becomes very useful in studying the impact of contact spacing, proximity effect and process window in writing line-cut or contact features in CEBL applications. Based on a given design rule of contact hole size and spacing, we can determine the appropriate e-beam size and resist contrast to achieve good image contrast. The relationship between resist contrast and image contrast is discussed to estimate the process window in CEBL applications. Finally, the impact of electron forward scattering in resist is analyzed, including the effects of resist thickness and beam voltage selections. We determined that the influence of back scattered electrons is not a significant factor in CEBL applications when feature pattern density is less than 11%.

In this study we report a new method for direct-write maskless lithography using oxidized silicon layer induced by high repetition (MHz) ultrafast (femtosecond) laser pulses under ambient condition. The induced thin layer of predetermined pattern can act as an etch stop during etching process in alkaline etchants such as KOH. The proposed method can be leading to promising solutions for direct-write maskless lithography technique since the proposed method offers a higher degree of flexibility and reduced time and cost of fabrication which makes it particularly appropriate for rapid prototyping and custom scale manufacturing. A Scanning Electron Microscope (SEM), Micro-Raman, Energy Dispersive X-ray (EDX), optical microscope and X-ray diffraction spectroscopy (XRD) were used to evaluate the quality of oxidized layer induced by laser pulses.

The authors designed novel electron beam slim column cells that have the outer diameters of 60mm and 40mm in width for an e-beam exposure of patterns down to 12nm and below. The column has maximum magnetic flux density of less than 2.2Tesla in the pole-piece of objective lens. No magnetic saturation occurs in the lens. The 12-88% blur at shaped beam edges through the column is better than 12nm to expose 12nm 1:1 LS patterns. Calorific power by lens coil of the column is smaller than 200watt. This slim column cell of high resolution and small size will provide various types of electron beam exposure systems with single or multiple exposure columns.

Techniques to introduce of electron beam direct writing (EBDW) technology into the volume production lines for the 65 nm process technology are shown and discussed. In order to apply these techniques in a harmonious way, partial modifications to the current production line infrastructures are required, because those infrastructures have been optimized for the conventional photolithography technology. One of the large differences is with the alignment. For the gate layer, the appropriate solution is to have an additional process step to remove SiO2 material filled in the shallow trench isolation alignment marks before the patterning. For the dual damascene process at the metal layers, careful consideration of the choice between the indirect alignment or the direct alignment is necessary, when the metal layer is aligned to the previous via layer underneath. We expect that these techniques can be used for the advanced node devices as well, while some new structures would be applied on these devices. In addition to the optimizing the alignment mark structures, the appropriate adjustment of EBDW system parameters by advanced process control (APC) is required, in order to have enough overlay accuracy at the actual production use. Although such process control systems are normally optimized to photolithography, we have confirmed that APC system can be also used for the EBDW technology for appropriate overlay accuracy control. Furthermore, the alignment budget in our systems is created and the alignment accuracy in our future system is estimated based on it. Based on the findings from these discussions, we expect that the EBDW with e-beam-only alignment will be applicable for the production of the 11 nm half-pitch process technology node and the beyond.

To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count reduction is the essential key. All device circuits should be composed with predefined character parts and we call this methodology “CP element based design”. In our previous work, we presented following three concepts [2]. 1) Memory: We reported the prospects of affordability for the CP-stencil resource. 2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis. 3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated tracks and cutting points at the tile edges. In this paper, we will report the experimental proofs in these methodologies. In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1], we assumed total available CP stencil resource as 9000um². We should manage to layout all circuit macros within this restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput. In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance. For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design CP stencils to hit the target throughput within the area constraint. From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don’t need special CP design approach than legacy pattern matching CP extraction. From all these experimental results we get good prospects to the reality of full CP element based layout.

Proximity Effects in electron beam lithography impact feature dimensions, pattern fidelity and uniformity. Electron scattering effects are commonly addressed using a mathematical model representing the radial exposure intensity distribution induced by a point electron source, commonly named Point Spread Function (PSF). PSF models are usually employed for correcting “short-range” and “long-range” backscattering effects up to 10μm to 15μm. It is well known that there are also some process related phenomena impacting pattern uniformity that have a wider range (fogging, chemical mechanical polishing -CMP- effects, etc.) which impacts up to a few millimeters or more. There are a number of commercial strategies for mitigating such long range effects based on data density. However, those traditional ones are usually performed within a single chip on a reticle field and ignore the presence of adjacent fields, neglecting their influence. Full field reticles can contain several different designs or arrayed chips in a multitude of layout placements. Reticle level jobdeck placing each design at specific sites, independent of each other can be used to account for the density of each pattern that has a relative impact on its neighbors, even if they are several millimeters away from offending data. Therefore, full field density analysis accounting for scribe frames and all neighboring patterns is required for reaching fidelity control requirements such as critical dimension (CD) and line end shortening (LES) on the full plate. This paper describes a technique to compensate long range effects going across chip boundaries to the full reticle exposure field. The extreme long range effects are also represented with a model that is calibrated according to the characteristics of the user‟s process. Data correction can be based on dose and geometry modulation. Uniform pattern dimensional control matching the user's specific process long range variability can be achieved with the techniques described in this paper.

Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) technology targeting high-volume 10 nm logic performance. There are several potential applications for E-Beam Direct Write Lithography in high volume manufacturing (HVM) Lithography. They range from writing full critical layers to the use as complementary lithography in order to write cut masks for multiple patterning optical lithography. Two of the potential applications for REBL with specific requirements on the writing strategy are contact layer and cut mask lithography. For these two applications the number of electrons writing a single feature can be a concern if the resist sensitivity is high and the process latitude is small. This paper will share calculations with respect to the needed and expected shot noise, dose and focus latitude performance of a proposed REBL lithography system. The simulated results will be compared to data taken on test structures. Predicted performance based on the simulations and test results of a potential REBL system for contact layers and cut mask applications will be discussed.

Since multi electron beam exposure has become a serious contender for next generation mask making, proximity- and process effect corrections (PEC) need to be adapted to this technology. With feature sizes in the order of the short-range blurs (resist and tool), contrast enhancements need to be combined with standard linearity corrections. Different PEC strategies are reviewed and compared with respect to their suitability for multi-beam exposure. This analysis recommends a hybrid approach that combines the benefits of shape- and dose PEC and is optimally applicable for multibeam exposure. Exposure results on the proof-of-concept 50keV electron multi-beam mask exposure tool (eMET POC) and a standard 50 kV vector shaped beam tool (VSB) are shown to verify that the combined PEC with overdose contrast enhancement covers the whole pattern range from isolated to opaque.

A spacer patterning technique using a poly-Si micro-feature and a SiO₂ spacer has been demonstrated to achieve sub-22 nm structures with conventional semiconductor equipments. The sub-22 nm structures have been fabricated by a plasma etching of Si substrate with a spacer oxide mask of which dimension is accurately controlled by the deposited film thickness. The profile of the Si nano-feature was influenced by an O₂ flow rate during Si etching in inductively coupled plasma (ICP). As the O₂ flow rate was decreased, the etch profile was improved vertically even though the etch rate of Si was slightly decreased. We obtained a 6-inch Si template with both nano- and micro-features of positive shape used for a master mold in nanoimprint lithography (NIL). The nano-sized Si features showed 22-nm width and 145-nm height with the slope of 87°. Further size reduction by anisotropic wet etching with KOH solution was also investigated.

Oblique angle metal deposition has been combined with high aspect ratio imprinted structures to create wire grid polarizers (WGP’s) for use as polarization recyclers in liquid crystal displays. The process of oblique deposition was simulated to determine optimal feature profile and deposition geometry. The optical results for the oblique deposition WGP show contrast comparable to a conventionally etched WGP. The next steps to the fabrication of meter sized WGP are proposed.

The negative tone development (NTD) process has proven benefits for superior imaging performance in 193nm lithography. Shrink materials, such as AZ® RELACS® have found widespread use as a resolution enhancement technology in conventional 248nm (DUV), 193 nm dry (ArF) and 193 nm immersion (ArFi) lithography. Surfactant rinses, such as AZ® FIRM® are employed as yield enhancement materials to improve the lithographic performance by avoiding pattern collapse, eliminating defects, and improving CDU. This paper describes the development and recent achievements obtained with new shrink and rinse materials for application in NTD patterning processes.

The industry’s march towards higher transistor density has called for an ever-increasing number of interconnect levels in logic devices. The historic transition from aluminum to copper was necessary in reducing timing delays while future technology nodes presents an opportunity for new materials and patterning techniques. One material for consideration is graphene, a single atomic layer of carbon atoms. Graphene is known to have excellent electrical properties [1], driving strong interest in its integration into the wafer fabrication processes for future electronics [2], and its ballistic transport properties give promise for use in on-chip interconnects [3]. This study demonstrates the feasibility of a direct electron beam lithography technique to pattern sub-5nm metallic graphene ribbons, without using a mask or photoresist, to act as next generation interconnects. Sub-5nm monolayer and multilayer graphene ribbons were patterned using a focused electron beam in a transmission electron microscope (TEM) through direct knock-on ejection of carbon atoms. These ribbons were measured during fabrication to quantify their electrical performance. Multilayered graphene nanoribbons were found to sustain current densities in excess of 10⁹ A/cm², orders of magnitude higher than copper, while monolayer graphene provides comparable performance to copper but at the level of a single atomic layer. High volume manufacturing could utilize wafer-size chemical vapor deposition (CVD) graphene [4] transferred directly onto the substrate paired with a direct write multi-beam tool to knock off carbon atoms for patterning of nanometer sized interconnects. The patterning technique introduced here allows for the fabrication of small foot-print high performance next generation graphene interconnects that bypass the use of a mask and resist process.