Bit-Serial Architectures For Parallel Arrays

P. B. Denyer; S. G. Smith

doi:10.1117/12.960499

28 July 1986 Bit-Serial Architectures For Parallel Arrays

P. B. Denyer, S. G. Smith

Proceedings Volume 0614, Highly Parallel Signal Processing and Architectures; (1986) https://doi.org/10.1117/12.960499
Event: O-E/LASE'86 Symposium, 1986, Los Angeles, CA, United States

Abstract

We review the use of bit-serial circuit techniques for parallel machine architectures. We identify the key concept of functional parallelism and present some examples of its application, including its use in the FIRST silicon compiler. We introduce a new com-parison of LSB-first and MSB-first serial techniques, and find that the latter approach may have distinct advantages for more complex arithmetic functions (like divide and square root), and for a general floating-point element. Finally, we review the serial programmable array processors and find significant future potential as a general computing substrate.

Citation Download Citation

P. B. Denyer and S. G. Smith "Bit-Serial Architectures For Parallel Arrays", Proc. SPIE 0614, Highly Parallel Signal Processing and Architectures, (28 July 1986); https://doi.org/10.1117/12.960499

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available