Processing Methods for the Fabrication of Sub-0.25 µm GaAs Heterostructure Devices and Circuits

D. J. Resnick; F. Ren; D. M. Tennant; R. F. Kopf

doi:10.1117/12.968519

1 August 1989 Processing Methods for the Fabrication of Sub-0.25 µm GaAs Heterostructure Devices and Circuits

D. J. Resnick, F. Ren, D. M. Tennant, R. F. Kopf

Proceedings Volume 1089, Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lithographies VIII; (1989) https://doi.org/10.1117/12.968519
Event: 1989 Santa Clara Symposium on Microlithography, 1989, San Jose, CA, United States

Abstract

Interest in GaAs Heterostructure FETs has increased significantly in recent years because of the potential benefits in circuit performance over conventional MESFET devices. Short propagation delays have been observed in half micron and sub-half micron logic circuits with little evidence of short channel effects. The purpose of this work was to develop a process for defining sub-half micron gates and to examine the device performance limitations of Heterostructure FETs as gate lengths were decreased below 0.25 μm. The methods for reliably defining a half micron lift-off gate have been described previously 2. A modified lift-off process has been developed in order to define gate features as small as 0.10 μm. The gates were produced using a trilevel resist consisting of EBR-9 as the imaging resist. The intermediate level consisted of germanium. PMGI was used as the planarizing resist. For gate lengths below 0.25 μm, a JEOL JBX-5D11 was used to expose the EBR-9. Exposure doses ranged from 40 to 60 pC/cm² at 50keV. The address and spot size were both 250Å. Site by site alignment was used to register the gate to the underlying ohmic level. Both the method used to define the gate level and the resultant process latitude will be discussed. The techniques used to avoid damage to the underlying heterostructure layers during the reactive ion etch of the PMGI resist will also be presented. In addition, the effect on device performance caused by altering the underlying heterostructure layer will be discussed. Finally, the performance of devices as a function of gate length will be presented.

Citation Download Citation

D. J. Resnick, F. Ren, D. M. Tennant, and R. F. Kopf "Processing Methods for the Fabrication of Sub-0.25 µm GaAs Heterostructure Devices and Circuits", Proc. SPIE 1089, Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lithographies VIII, (1 August 1989); https://doi.org/10.1117/12.968519

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