Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

S. M. Yasser Sherazi; Miroslav Cupak; P. Weckx; O. Zografos; D. Jang; P. Debacker; D. Verkest; A. Mocuta; R. H. Kim; A. Spessot; J. Ryckaert

doi:10.1117/12.2514569

27 March 2019 Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

S. M. Yasser Sherazi, Miroslav Cupak, P. Weckx, O. Zografos, D. Jang, P. Debacker, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, J. Ryckaert

Author Affiliations +

Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096202 (2019) https://doi.org/10.1117/12.2514569
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared to the previous node definitions [1,2]. The overall industry trend of poly pitch scaling is slowing down, due to difficulties in keeping pace with device performance and yield issues. However, the metal pitch continues to scale down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that can enable an N3 technology node by using Design-Technology cooptimization (DTCO).

Conference Presentation

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S. M. Yasser Sherazi, Miroslav Cupak, P. Weckx, O. Zografos, D. Jang, P. Debacker, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, and J. Ryckaert "Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096202 (27 March 2019); https://doi.org/10.1117/12.2514569

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