Challenges for spacer and source/drain cavity patterning in CFET devices

G. Mannaert; H. Mertens; M. Hosseini; S. Demuynck; V. T. H. Nguyen; B. T. Chan; F. Lazzarino

doi:10.1117/12.2658073

1 May 2023 Challenges for spacer and source/drain cavity patterning in CFET devices

G. Mannaert, H. Mertens, M. Hosseini, S. Demuynck, V. T. H. Nguyen, B. T. Chan, F. Lazzarino

Proceedings Volume 12499, Advanced Etch Technology and Process Integration for Nanopatterning XII; 1249908 (2023) https://doi.org/10.1117/12.2658073
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

In a complementary-FET (CFET), n- and p- type transistors are stacked on top of each other. This stacking approach results in very high aspect ratio vertical features which brings critical challenges for nanosheet (NSH), gate, spacer, and source/drain (S/D) cavity patterning. Silicon nitride spacers are commonly used to electrically isolate and protect the silicon gate during S/D epitaxial growth and to precisely define the channel length (Lg) [1-4]. In this work, we will discuss the spacer film opening, the optimization of the S/D cavity profile and propose options to reduce the gate hard mask consumption. We were able to straighten the S/D cavity profile in the SiGe superlattice substrate by tuning specific process parameters, during the various etch and over-etch steps of the stack. Chemical analysis of the sidewall of the cavity, by TEM/EDS, confirmed that the formation of a passivation oxi-nitride compound is key to achieve vertical cavity profile. The chemical mapping of the cavity was done through the Si and SiGe25% sheets. A Si, O and N containing passivation layer is present in the cavity which seems to be thicker at the top and thinner at the bottom of the cavity. Furthermore, polymer capping methods were investigated to reduce the consumption of oxide hard mask (HM) during spacer etch. Process optimization for the cavity shape in the S/D recess etch was conducted using TEM characterization.

Conference Presentation

Citation Download Citation

G. Mannaert, H. Mertens, M. Hosseini, S. Demuynck, V. T. H. Nguyen, B. T. Chan, and F. Lazzarino "Challenges for spacer and source/drain cavity patterning in CFET devices", Proc. SPIE 12499, Advanced Etch Technology and Process Integration for Nanopatterning XII, 1249908 (1 May 2023); https://doi.org/10.1117/12.2658073

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available