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Spin-orbit torque (SOT) devices are being pursued for various memory and in-memory compute applications. At nanoscale dimensions, electric current flowing through the SOT channel can be non-uniform due to incomplete current redistribution. Such effects were ignored in the prior modeling works. We present a comprehensive modeling framework for SOT devices that capture the effects of incomplete current redistribution along with interface spin-mixing, and non-uniform resistivity. Our transfer matrix-based formalism along with finite element simulations can account for any local variation in resistivity and spin diffusion length along with accounting for various spin-scattering mechanisms. In addition, we quantify the optimal SOT layer thickness to minimize the write energy in terms of its resistivity and spin diffusion length. To improve the bit density of SOT magnetic random-access memory (MRAM), we explore area saving schemes based on sharing SOT channel among multiple magnetic tunnel junctions (MTJs) with the help of voltage-controlled magnetic anisotropy (VCMA) effect and spin-transfer torque (STT). Using micromagnetic simulations, we study various tradeoffs among write time, current, error rate, and the number of MTJs. Our results show that the number of MTJs on the shared SOT channel is limited by the voltage drop over the SOT channel and write error rate, and having more than 4 MTJs on a SOT channel poses major challenges in terms of reliability.
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