Poster + Paper
21 August 2024 The VERITAS 2.3 readout ASIC for the ATHENA Wide Field Imager
Anna-Katharina Schweingruber, Sven Herrmann, Peter Orel, Ajay Kumar Dakshinamurthy, Astrid Mayr, Johannes Müller-Seidlitz, Jonas Reiffers, Sebastian Albrecht, Hermine Schnetler, Steven W. Allen, Glenn Morris
Author Affiliations +
Conference Poster
Abstract
VERITAS 2.3 is a further step in the development of the VERITAS (VErsatile Readout based on Integrated Trapezoidal Analog Shapers) ReadOut Integrated Circuit (ROIC) architecture designed for high-speed, lownoise readout of the DEPFET detectors in the Wide Field Imager on ESA’s ATHENA X-ray satellite. The chip includes 64 channels, delivering a short processing time of 2.5 μs per readout while targeting a system noise of 3 e ENC RMS, enabling nearly Fano-limited spectroscopic performance. While the new chip still uses previous versions’ proven 0.35 μm CMOS technology node, we have employed new foundry and process options for better manufacturability and improved reliability. An overview of the design and development of VERITAS 2.3 is presented, along with the first standalone functionality and performance measurements conducted using a dedicated ASIC test setup.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Anna-Katharina Schweingruber, Sven Herrmann, Peter Orel, Ajay Kumar Dakshinamurthy, Astrid Mayr, Johannes Müller-Seidlitz, Jonas Reiffers, Sebastian Albrecht, Hermine Schnetler, Steven W. Allen, and Glenn Morris "The VERITAS 2.3 readout ASIC for the ATHENA Wide Field Imager", Proc. SPIE 13093, Space Telescopes and Instrumentation 2024: Ultraviolet to Gamma Ray, 130934D (21 August 2024); https://doi.org/10.1117/12.3018879
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KEYWORDS
Analog electronics

Field effect transistors

Tunable filters

Sensors

Electronic filtering

Signal filtering

Multiplexers

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