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We explore application of an original hardware design methodology based on explicit decoupling of computations and transaction flow control to neuromorphic processor microarchitecture. We have developed “Neuromorphix” class library that provides a custom abstraction level for synthesizable neuromorphic processors descriptions. This abstraction level is based on transactions traversing through pipelined structures, computing data while being in-flight within the hardware structures, and managed by automatically generated control infrastructure. This control infrastructure includes a block of sequential neuron selector, spikes scheduling buffers, control flow protocols, memory architecture for static and dynamic neuron parameters, which together orchestrate data processing and communication within the hardware. The library is integrated in ActiveCore hardware generation framework previously developed by the authors. Experimental designing of FPGA-based prototypes shows that the proposed approach allows to efficiently separate non-intuitive aspects of hardware microarchitecture (requiring highly specific competence for implementation) from trivial application-specific logic and reuse of complex design decisions in hardware microarchitecture, while preserving full control over internals of synthesized hardware and obtaining competitive characteristics of generated designs. |
