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4 December 2024 Digital readout integrated circuit for small pixel infrared focal plane arrays
Douming Hu, Libin Yao, Nan Chen, Jiqing Zhang, Jicun Wang, Kesong Chen
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Proceedings Volume 13283, Conference on Spectral Technology and Applications (CSTA 2024); 132832T (2024) https://doi.org/10.1117/12.3036950
Event: Conference on Spectral Technology and Applications (CSTA 2024), 2024, Dalian, China
Abstract
This paper proposes a digital readout integrated circuit (DROIC) for a small pixel MW IRFPA application with a high signal-to-noise ratio (SNR). The storable charge should be substantial enough to maintain a high SNR. A tiny direct injection structure is used for a 7.5 µm pixel pitch. Second, MOSFET and MIM capacitors are employed for integral capacitance to achieve high well capacity. Furthermore, the well capacity issue is addressed by sequentially sharing a bigger capacitor between every two pixels of the arrays. The pixel signal is transferred to the column-level ADC for quantification. DROIC's ADC supports 12 or 13-bit resolution settings to choose from. Following conversion, the digital data of the signal is transferred to the off-chip via multiple output channels. The simulation indicates that the DROIC noise is 1.26 LSBrms at 77K, and the entire well capacity can reach 0.75Me- and 1.5Me- (at 1×2 binning mode), which is advantageous for NETD. The simulation shows that the suggested DROIC is suitable for small-pixel pitch infrared FPAs.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
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Douming Hu, Libin Yao, Nan Chen, Jiqing Zhang, Jicun Wang, and Kesong Chen "Digital readout integrated circuit for small pixel infrared focal plane arrays", Proc. SPIE 13283, Conference on Spectral Technology and Applications (CSTA 2024), 132832T (4 December 2024); https://doi.org/10.1117/12.3036950
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KEYWORDS
Analog to digital converters
Signal to noise ratio
Readout integrated circuits
Infrared detectors
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