Challenges of using advanced multichip packaging for next generation spaceborne computers

Thomas J. Moravec

doi:10.1117/12.25576

1 April 1991 Challenges of using advanced multichip packaging for next generation spaceborne computers

Thomas J. Moravec

Proceedings Volume 1390, Microelectronic Interconnects and Packages: System and Process Integration; (1991) https://doi.org/10.1117/12.25576
Event: Advances in Intelligent Robotics Systems, 1990, Boston, MA, United States

Abstract

The Strategic Defense Initiative and other space programs have accelerated the requirement to put fast powerful computers with large memory requirements into space on various satellites. Operation during launch and in space environments places some challenging requirements on siliconbased electronics. They must survive large thermal and mechanical shocks and exposure to radiation. This paper presents one of the approaches taken to date to build spaceborne computers with high density multi-chip packaging technology.

Citation Download Citation

Thomas J. Moravec "Challenges of using advanced multichip packaging for next generation spaceborne computers", Proc. SPIE 1390, Microelectronic Interconnects and Packages: System and Process Integration, (1 April 1991); https://doi.org/10.1117/12.25576

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available