Parallel butterfly algorithm and VLSI architectures for image decorrelation

Tinku Acharya; Amar Mukherjee

doi:10.1117/12.174967

2 May 1994 Parallel butterfly algorithm and VLSI architectures for image decorrelation

Tinku Acharya, Amar Mukherjee

Proceedings Volume 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies; (1994) https://doi.org/10.1117/12.174967
Event: IS&T/SPIE 1994 International Symposium on Electronic Imaging: Science and Technology, 1994, San Jose, CA, United States

Abstract

We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the- art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favorably comparable to the JPEG baseline lossless image compression schemes. We also discuss the parallelization issues of the JPEG baseline standard still compression schemes and their difficulties.

Citation Download Citation

Tinku Acharya and Amar Mukherjee "Parallel butterfly algorithm and VLSI architectures for image decorrelation", Proc. SPIE 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies, (2 May 1994); https://doi.org/10.1117/12.174967

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