Effects of grid-placed contacts on circuit performance

Jun Wang; Alfred K. K. Wong

doi:10.1117/12.485279

2 July 2003 Effects of grid-placed contacts on circuit performance

Jun Wang, Alfred K. K. Wong

Proceedings Volume 5043, Cost and Performance in Integrated Circuit Creation; (2003) https://doi.org/10.1117/12.485279
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

The impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is studied. Although snapping contacts to grid adds restrictions during layout design, smaller circuit area can be achieved by careful selection of the grid pitch, raising the lower limit of transistor width, applying double exposure, and shrinking the minimum contact pitch enabled by more effective application of resolution enhancement technologies. The technique is demonstrated on the contact level of 250-nm standard cells with the minimum contact pitch shrunk by 10%. The area change of 84 cells ranges from -20% to 25% with a median decrease of 5%. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2% respectively. Delay and power consumption are also estimated to decrease with area.

Citation Download Citation

Jun Wang and Alfred K. K. Wong "Effects of grid-placed contacts on circuit performance", Proc. SPIE 5043, Cost and Performance in Integrated Circuit Creation, (2 July 2003); https://doi.org/10.1117/12.485279

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