Paper
9 December 2004 FPGA implementation of real-time adaptive image thresholding
Author Affiliations +
Abstract
A general purpose FPGA architecture for real-time thresholding is proposed in this paper. The hardware architecture is based on a weight-based clustering threshold algorithm that takes the thresholding as a problem of clustering background and foreground pixels. This method employs the clustering capability of a two-weight neural network to find the centriods of the two pixel groups. The image threshold is the average of these two centriods. The proposed method is an adaptive thresholding technique because for every input pixel the closest weight is selected for updating. Updating is based on the difference between the input pixel gray level and the associated weight, scaled by a learning rate factor. The hardware system is implemented on a FPGA platform and consists of two pipelined functional blocks. While the first block is obtaining the threshold value for current frame, another block is applying the threshold value to the previous frame. This parallelism and the simple hardware component of both blocks make this approach suitable for real-time applications, while the performance remains comparable with the Otsu technique frequently used in off-line threshold determination. Results from the proposed algorithm are presented for numerous examples, both from simulations and experimentally using the FPGA. Although the primary application of this work is to centroiding of laser spots, its use in other applications will be discussed.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Elham Ashari and Richard I. Hornsey "FPGA implementation of real-time adaptive image thresholding", Proc. SPIE 5578, Photonics North 2004: Photonic Applications in Astronomy, Biomedicine, Imaging, Materials Processing, and Education, (9 December 2004); https://doi.org/10.1117/12.566861
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Cited by 11 scholarly publications.
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KEYWORDS
Image processing

Field programmable gate arrays

Signal processing

Binary data

Neural networks

Artificial neural networks

Data storage

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