Arithmetic Frequency Synthesis Using A Systolic Array

Douglas N. Curry

doi:10.1117/12.949708

4 January 1986 Arithmetic Frequency Synthesis Using A Systolic Array

Douglas N. Curry

Proceedings Volume 0564, Real-Time Signal Processing VIII; (1986) https://doi.org/10.1117/12.949708
Event: 29th Annual Technical Symposium, 1985, San Diego, United States

Abstract

A systolic clock generator has been designed and built with 320 identical computing elements on a single VLSI chip which can provide a considerable increase in the rate at which an accumulator may be used to produce a variable frequency clock. A single Arithmetic Frequency Synthesizer (AFS) chip (with appropriate external circuitry), having the equivalent of sixteen accumulators, can provide a programmable clock at frequencies sixteen times greater than that obtainable with a single accumulator. By using up to four AFS chips in parallel, a 64 times improvement of the system output clock frequency may be obtained.

Citation Download Citation

Douglas N. Curry "Arithmetic Frequency Synthesis Using A Systolic Array", Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); https://doi.org/10.1117/12.949708

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