Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches

Nishrin Kachwala; Walter Iandolo; Travis Brist; Rick Farnbach

doi:10.1117/12.602539

5 May 2005 Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches

Nishrin Kachwala, Walter Iandolo, Travis Brist, Rick Farnbach

Proceedings Volume 5756, Design and Process Integration for Microelectronic Manufacturing III; (2005) https://doi.org/10.1117/12.602539
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. Design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect.

Citation Download Citation

Nishrin Kachwala, Walter Iandolo, Travis Brist, and Rick Farnbach "Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches", Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); https://doi.org/10.1117/12.602539

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