Divgen: a divider unit generator

Romain Michard; Arnaud Tisserand; Nicolas Veyrat-Charvillon

doi:10.1117/12.614419

16 September 2005 Divgen: a divider unit generator

Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon

Proceedings Volume 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV; 59100M (2005) https://doi.org/10.1117/12.614419
Event: Optics and Photonics 2005, 2005, San Diego, California, United States

Abstract

In this work, we present a tool that generates division hardware units. This generator, called divgen, allows a fast and wide space exploration in circuits that involve division operations. The generator produces synthesizable VHDL descriptions of optimized division units for various algorithms and parameters. The results of our generator have been demonstrated on FPGA circuits.

Citation Download Citation

Romain Michard, Arnaud Tisserand, and Nicolas Veyrat-Charvillon "Divgen: a divider unit generator", Proc. SPIE 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV, 59100M (16 September 2005); https://doi.org/10.1117/12.614419

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