FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

Chun-Chi Yu; Ming-Feng Shieh; Erick Liu; Benjamin Lin; Jonathan Ho; Xin Wu; Petrisor Panaite; Manoj Chacko; Yunqiang Zhang; Wen-Kang Lei

doi:10.1117/12.637426

9 November 2005 FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Jonathan Ho, Xin Wu, Petrisor Panaite, Manoj Chacko, Yunqiang Zhang, Wen-Kang Lei

Author Affiliations +

Proceedings Volume 5992, 25th Annual BACUS Symposium on Photomask Technology; 59925A (2005) https://doi.org/10.1117/12.637426
Event: SPIE Photomask Technology, 2005, Monterey, California, United States

Abstract

In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

Citation Download Citation

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Jonathan Ho, Xin Wu, Petrisor Panaite, Manoj Chacko, Yunqiang Zhang, and Wen-Kang Lei "FPGA chip performance improvement with gate shrink through alternating PSM 90nm process", Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 59925A (9 November 2005); https://doi.org/10.1117/12.637426

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
13 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Photomasks

Optical proximity correction

Critical dimension metrology

Lithography

Design for manufacturing

Halftones

Manufacturing

Show All Keywords

Keywords/Phrases

Search In:

Publication Years