Modelling an optically interconnected FPGA for reconfigurable computing architectures

G. A. Russell; C. J. Moir; J. F. Snowdon

doi:10.1117/12.662718

21 April 2006 Modelling an optically interconnected FPGA for reconfigurable computing architectures

G. A. Russell, C. J. Moir, J. F. Snowdon

Proceedings Volume 6185, Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration; 61850I (2006) https://doi.org/10.1117/12.662718
Event: SPIE Photonics Europe, 2006, Strasbourg, France

Abstract

A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits^-1 system was found to be 158.5ns.

Citation Download Citation

G. A. Russell, C. J. Moir, and J. F. Snowdon "Modelling an optically interconnected FPGA for reconfigurable computing architectures", Proc. SPIE 6185, Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration, 61850I (21 April 2006); https://doi.org/10.1117/12.662718

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