A generic method for the detection of electrically superfluous layout features

Markus Hofsaess; Thomas Roessler; Eva Nash

doi:10.1117/12.687856

20 October 2006 A generic method for the detection of electrically superfluous layout features

Markus Hofsaess, Thomas Roessler, Eva Nash

Proceedings Volume 6349, Photomask Technology 2006; 634916 (2006) https://doi.org/10.1117/12.687856
Event: SPIE Photomask Technology, 2006, Monterey, California, United States

Abstract

"Sub-resolution assist features" (SRAFs) are a standard "resolution enhancement technique" (RET) to ensure the lithography process window of narrow lines for critical mask levels. Since placement rules for SRAFs commonly demand a fixed, constant separation from the edges of the main features to be assisted, small jogs and notches in the layout of the main features force an SRAF interruption. As a consequence, locally the process window is reduced. In addition, jogs and notches increase the data amount and may cause an increase of run time of "design rule check" (DRC), "optical proximity correction" (OPC), and "mask data preparation" (MDP). In most cases, these jogs and notches are completely unnecessary for the electrical functionality of the circuit and the design rule compliance of the layout. In order to detect such superfluous layout features and give the physical designer the opportunity to remove them, a new approach to design rule checking was developed. This approach is based on the decomposition of the layout of one mask level into its basic geometrical features (e.g., corners, line ends, junctions) and a subsequent classification of these features according to their topology under consideration of electrically related other mask levels (e.g., metal + via = contact pad). We describe the implementation of a generic DRC for the detection of jogs and notches using this approach and highlight the stability and ease of maintenance of this method.

Citation Download Citation

Markus Hofsaess, Thomas Roessler, and Eva Nash "A generic method for the detection of electrically superfluous layout features", Proc. SPIE 6349, Photomask Technology 2006, 634916 (20 October 2006); https://doi.org/10.1117/12.687856

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
9 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

SRAF

Photomasks

Optical proximity correction

Transistors

Resolution enhancement technologies

Lithography

Metals

Show All Keywords

Keywords/Phrases

Search In:

Publication Years