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A half-node process has been routinely used to deliver incremental improvements in process control and hardware
availability in order to continue Moore's Law. Traditionally, due to the imaging requirements, parameters such as
numerical aperture and partial coherence were not set to their maximum resolution settings, thus leaving room in
hardware and RET recipes to accommodate incremental imaging requirements. However, as hardware availability and
computational lithography methods are stressed to the maximum of their capabilities to deliver the next technology
nodes, it is worth asking the question if such optical shrinks continue to be viable moving forward. Already 28nm
layouts scaled down from the original 32nm layouts are starting to show signs of configuration limitations dictated by
the available imaging hardware.
In this paper we show that two-dimensional features determine the feasibility of migrating successfully to the next halfnode
even when one-dimensional metrics suggest that such migration should be possible. While it has been proposed
that methodologies that are based on fabrics can guarantee composability and are intrinsically easier to migrate to
smaller nodes, such approaches are mostly valid for processes in which the frequency distribution of the object to be
imaged remains compatible with the hardware and RET of choice. This paper suggests that the distribution and extent
of the layout fabric discontinuities present one of the major hurdles to composability. In other words, it is not only
necessary to determine the best pitch and width of the underlying fabric it becomes crucial to determine the distribution
of the discontinuities present in the layout to build discrete devices.
Given that the feasibility of a half-node process is determined mostly by its ability to achieve denser patterns without
non-trivial layout modifications, in this paper we show that it is important to start looking at the explicit layout
configuration aspects that determine layout printability. We have selected a pair of prototypical layout configurations
common across all technology nodes of interest and have determined their intrinsic failure conditions for a given
process.
The results indicate that for a well padded 32nm process it may still be possible to perform an optical 28nm shrink with
only a minimum of manual intervention, assuming that certain layout configurations are removed or carefully
monitored during production. However, the nature of the analysis suggest that moving forward to 22nm and in the
absence of higher-resolution hardware (i.e. EUV) optical shrinks that require little or no layout modifications to the
desired patterns to be printed may no longer be possible.
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