Sensitivity of LWR and CD linearity to process conditions in active area

Guy Ayal; Elena Malkes; Efraim Aharoni; Shimon Levi; Amit Siany; Ofer Adan; Eitan Shauly; Yosi Shacham-Diamand

doi:10.1117/12.879322

20 April 2011 Sensitivity of LWR and CD linearity to process conditions in active area

Guy Ayal, Elena Malkes, Efraim Aharoni, Shimon Levi, Amit Siany, Ofer Adan, Eitan Shauly, Yosi Shacham-Diamand

Proceedings Volume 7971, Metrology, Inspection, and Process Control for Microlithography XXV; 79711Q (2011) https://doi.org/10.1117/12.879322
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

LWR and CD linearity are both a major concern in the interpretation of drawn devices to actual structures on Si, and even more when translating to expected currents (both driven current and leakage current). Both of them have long ago been shown to be sensitive to process (especially lithographic) conditions, but usually not comparatively and, even more seldom are the final (etched) results thus related to the lithography process. Following our previous work on the sensitivities of LER and LWR to layout, we set out to research whether these sensitivities are themselves sensitive to process changes which tend to affect LER and LWR. As a logical conclusion, we expected that process changes which tend to worsen roughness will increase the dependence of the roughness on layout effects - that the outcome will be addible. Measurements were done in Active Area (a.k.a. STI definition) layer. Results show very interesting dependence of roughness and CD linearity (dependence of measured CDs on drawn CDs) of long dense resistors. Process changes that tended to make roughness worse, also had significant impact on the linearity, making it surprisingly more accurate at the low CD regime, but with significantly more variance.

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Guy Ayal, Elena Malkes, Efraim Aharoni, Shimon Levi, Amit Siany, Ofer Adan, Eitan Shauly, and Yosi Shacham-Diamand "Sensitivity of LWR and CD linearity to process conditions in active area", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79711Q (20 April 2011); https://doi.org/10.1117/12.879322

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KEYWORDS

Line width roughness

Cadmium

Line edge roughness

Resistors

Transistors

Lithography

Critical dimension metrology

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