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As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after
optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by
k1 factor. To guarantee the imaging fidelity, resolution enhancement technologies (RET) such as off-axis illumination
(OAI), different types of phase shift masks and OPC technique have been developed. In case of model-based OPC, to
cross-confirm the contour image versus target layout, post-OPC verification solutions continuously keep developed -
contour generation method and matching it to target structure, method for filtering and sorting the patterns to eliminate
false errors and duplicate patterns. The way to detect only real errors by excluding false errors is the most important
thing for accurate and fast verification process - to save not only reviewing time and engineer resource, but also whole
wafer process time and so on. In general case of post-OPC verification for metal-contact/via coverage (CC) check,
verification solution outputs huge of errors due to borderless design, so it is too difficult to review and correct all points
of them. It should make OPC engineer to miss the real defect, and may it cause the delay time to market, at least.
In this paper, we studied method for increasing efficiency of post-OPC verification, especially for the case of
CC check. For metal layers, final CD after etch process shows various CD bias, which depends on distance with
neighbor patterns, so it is more reasonable that consider final metal shape to confirm the contact/via coverage. Through
the optimization of biasing rule for different pitches and shapes of metal lines, we could get more accurate and efficient
verification results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase
efficiency of OPC verification process by using simple biasing rule to metal layout instead of etch model application is
presented.
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