Error-rate prediction for programmable circuits: methodology, tools and studied cases

Raoul Velazco

doi:10.1117/12.2015391

29 May 2013 Error-rate prediction for programmable circuits: methodology, tools and studied cases

Raoul Velazco

Proceedings Volume 8725, Micro- and Nanotechnology Sensors, Systems, and Applications V; 872519 (2013) https://doi.org/10.1117/12.2015391
Event: SPIE Defense, Security, and Sensing, 2013, Baltimore, Maryland, United States

Abstract

This work presents an approach to predict the error rates due to Single Event Upsets (SEU) occurring in programmable circuits as a consequence of the impact or energetic particles present in the environment the circuits operate. For a chosen application, the error-rate is predicted by combining the results obtained from radiation ground testing and the results of fault injection campaigns performed off-beam during which huge numbers of SEUs are injected during the execution of the studied application. The goal of this strategy is to obtain accurate results about different applications’ error rates, without using particle accelerator facilities, thus significantly reducing the cost of the sensitivity evaluation. As a case study, this methodology was applied a complex processor, the Power PC 7448 executing a program issued from a real space application and a crypto-processor application implemented in an SRAM-based FPGA and accepted to be embedded in the payload of a scientific satellite of NASA. The accuracy of predicted error rates was confirmed by comparing, for the same circuit and application, predictions with measures issued from radiation ground testing performed at the cyclotron Cyclone cyclotron of HIF (Heavy Ion Facility) of Louvain-la-Neuve (Belgium).

Citation Download Citation

Raoul Velazco "Error-rate prediction for programmable circuits: methodology, tools and studied cases", Proc. SPIE 8725, Micro- and Nanotechnology Sensors, Systems, and Applications V, 872519 (29 May 2013); https://doi.org/10.1117/12.2015391

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