New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications

Wei Zhou; Darcy Hart

doi:10.1117/12.2026963

20 September 2013 New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications

Wei Zhou, Darcy Hart

Proceedings Volume 8819, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors VII; 881907 (2013) https://doi.org/10.1117/12.2026963
Event: SPIE NanoScience + Engineering, 2013, San Diego, California, United States

Abstract

Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.

Citation Download Citation

Wei Zhou and Darcy Hart "New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications", Proc. SPIE 8819, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors VII, 881907 (20 September 2013); https://doi.org/10.1117/12.2026963

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