A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method

Pu Wang; Chuyang Hong; Qi Cheng; Yijian Chen

doi:10.1117/12.2085919

18 March 2015 A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method

Pu Wang, Chuyang Hong, Qi Cheng, Yijian Chen

Author Affiliations +

Proceedings Volume 9427, Design-Process-Technology Co-optimization for Manufacturability IX; 94270W (2015) https://doi.org/10.1117/12.2085919
Event: SPIE Advanced Lithography, 2015, San Jose, California, United States

Abstract

In this paper, we present a compact model to predict the pillar-edge-roughness (PER) effects on 3D vertical nanowire MOSFETs using the perturbation method. An analytic solution to 3D Poisson’s equation in the cylindrical coordinate with a perturbed boundary is obtained to describe the PER effects on the vertical channel potential. The induced variations of drain current, threshold voltage (V_th), and sub-threshold slope (SS) are calculated using the developed model. We also investigate the PER phase and frequency dependent behavior of the nanowire MOSFETs, and find that both phase and (angular) frequency of the PER function will significantly affect the device performance. Our model calculation results are compared with TCAD simulations and a good agreement between them is found. It is suggested that our metrology society needs to develop relevant measurement methodology to characterize the nanowire pillar-edge roughness at deep nanoscale.

Citation Download Citation

Pu Wang, Chuyang Hong, Qi Cheng, and Yijian Chen "A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270W (18 March 2015); https://doi.org/10.1117/12.2085919

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