Getting ready for EUV in HVM

Gerald Dicker; Diederik de Bruin; Brennan Peterson; Pieter Wöltgens; Boudewijn Sluijk; Peter Jenkins

doi:10.1117/12.2195622

4 September 2015 Getting ready for EUV in HVM

Gerald Dicker, Diederik de Bruin, Brennan Peterson, Pieter Wöltgens, Boudewijn Sluijk, Peter Jenkins

Proceedings Volume 9661, 31st European Mask and Lithography Conference; 96610F (2015) https://doi.org/10.1117/12.2195622
Event: 31st European Mask and Lithography Conference, 2015, Eindhoven, Netherlands

Abstract

The most exciting and continuous debate in our industry is how long Moore’s law will continue, and tightly connected to this is the discussion on when EUV Lithography will be introduced in microchip mass manufacturing. In this review paper, we analyze and extrapolate Moore’s law based on critical design pitches for Logic and Memory devices. We will focus in more detail on an aggressive option for the 7nm Logic node based on an extrapolation in accordance with Moore’s law. For this node, we will discuss and compare all-immersion vs immersion-EUV based litho manufacturing costs, complexity and restrictions and consolidate field expert statements on device performance tradeoffs. We will conclude with an outlook on the affordability of shrink based on node-on-node CapEx projections. Based on interactions with our customers and peers, we project Moore’s law to continue in the 2020s, and we predict that shrink will remain profitable. Manufacturing cost and complexity will be mitigated by the introduction of EUV lithography. The recent progress in EUV productivity will ensure cost effectiveness of EUV-based designs, creating a “sweet spot” for EUV introduction at the 7nm node.

Citation Download Citation

Gerald Dicker, Diederik de Bruin, Brennan Peterson, Pieter Wöltgens, Boudewijn Sluijk, and Peter Jenkins "Getting ready for EUV in HVM", Proc. SPIE 9661, 31st European Mask and Lithography Conference, 96610F (4 September 2015); https://doi.org/10.1117/12.2195622

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