Over last five decades, transistor physical scaling has been the primary enabler for semiconductor technology evolution. Benefit of scaling in transistor gate contact pitches and metal pitches translates into benefits at the circuit level, and the chip level. As the transistor scaling gets close to its scaling limit due to short channel effect and process limits, new forms of scaling emerge to further extend technology evolution. The talk will focus on Z-dimensional scaling as the driver for new era of logic technology evaluation. Z-dimensional scaling is featured with innovations beyond traditional technology scaling. It includes innovations at the transistor level by stacking, the interconnect and power distribution level by their re-arrangement at both sides of the transistors, and the packaging level by heterogenous integration. Vertically integrating these innovations opens a new domain for technology and product evolution for next several decades.

Patterning cost and complexity continues to rise with every node. Although EUV lithography has extended dimensional scaling, its limitations have required the industry to implement multi-EUV and other complex patterning schemes. Single exposure EUV patterning is limited by stochastic defects at sub-36nm pitch. Also, counter-scaling between pitch and tip-to-tip spacing limits how close patterned features can be packed in the non-preferred direction. Multi-EUV patterning schemes significantly increase cost while also introducing Edge Placement Errors (EPE). We discuss here an innovative pattern shaping capability which can elongate pre-defined line/space and hole patterns to address these challenges. We will discuss various process knobs including reactive chemistry and material selectivity which can be tuned to allow precision pattern shaping. We will also show how this capability can be used for sidewall processing for applications such as asymmetric spacer removal. Directional pattern shaping has the potential to be a powerful tool in the patterning engineer’s toolbox to help further extend Moore’s law.

For enabling better electrostatic control of short channel devices, gate-all-around (GAA) nanowire/nanosheet (NW/NS) field-effect transistors (FETs) may replace FinFET in 3nm logic technology node and beyond. Horizontally stacked NW/NS FETs are especially promising due to its excellent electrostatics, short channel control, increased active width, and gate length scaling. In order to enable further scaling of GAA FETs, imec has been developing forksheet (FS) FET as well as complementary FET (CFET). For the manufacturing of FS and CFETs, there are several new challenges which require isotropic and selective etching. In this work, we have been developed chemical isotropic dry etching for the several key process steps along with the integration flow, including Si/SiGe superlattice fin reveal, dielectric wall formation, local SOI formation, SiGe cavity etch as well as the dielectric etchback for the inner spacer formation, dummy gate removal and SiGe selective etch for the Si channel release

Tighter edge placement requirements for advanced nodes has driven model accuracy requirements, especially in the area of etch modeling. Etch model errors are becoming a larger part of the total model error and effects that could previously be ignored, now have to be addressed. To address systematic errors in etch modeling, new modeling techniques for etch modeling are presented, namely, Variable Edge Bias (VEB) model, the Reactive Ion Etch Variable Bias Model (RIE VEB), and finally, neural network assisted dual stage etch (N2E) model. The VEB RIE model enables the ability to represent trends relating to physical parameters, such as time and temperature into the model. To further improve model accuracy, a machine learning solution is introduced, which operates on the etch model’s residual error.

We present a multi-fidelity process simulator ‘VizGlow-MPS’ that combines well-established high-fidelity models with a reduced-order model surrogate. The high-fidelity model provides experimentally validated results for equipment operation that informs the reduced-order model that predicts results in a few minutes of wall-clock time. The approach constitutes a ‘digital twin’ for process reactors with multiple levels of fidelity that a process engineering can choose from. This approach is demonstrated on c-C4F8 inductively coupled plasma and pulsed CF4/H2 capacitively coupled plasma widely used in etching applications.

Quantum computing is one of the grand challenges of the 21st century and promises to transform almost every industry. As quantum computing technology exits the academic research phase into manufacturing, the goal is not to build single, unique qubits, but millions of interconnected, identical qubits capable of performing fully error corrected, general purpose calculations. Photon-based qubits offer a path to such a general-purpose machine by leveraging the mature silicon photonics high-volume manufacturing ecosystem. Creating quantum devices from silicon photonics components requires patterning innovation to bring leading-edge nanolithography to near macroscopic scale, a unique challenge for an industry where the future relies on progressive device shrink.

Nanosheet device architectures, such as nanosheet (NS), forksheet (FS), and complementary FET (CFET), are promising to replace FinFET (FF) and enable further CMOS scaling in 3nm CMOS technology node and beyond thanks to wider effective transistor width per footprint. Key differences in NS integration from FF integration exist in Si/SiGe multilayer active, inner spacer, channel release, and replacement metal gate (RMG) patterning. Si/SiGe multilayer active requires an etch process that does not damage SiGe, and low temperature fill & recess to reduce Ge diffusion. Inner spacer is a common important module for NS, FS, and CFET to reduce parasitic capacitance, where precise lateral etch control and high etch selectivity are necessary in Si or SiGe cavity selective etch and inner dielectric isotropic etch. Channel release is an essential process step to enable nanosheet architectures, which needs high selective SiGe or Si etch. A post clean without residue, surface roughness, and NS stiction is required. In RMG patterning, work function metal removal in NS-NS vertical space without N-P space increase is important, which is enabled by introducing sacrificial pattering cap layer and faster etch rate in WFM or sacrificial layer seams. FS improves scalability of N-P patterning in SD epi and RMG patterning by reducing hard mask (HM) patterning aspect ratio on dielectric wall. However, high HM etch selectivity to dielectric wall and HM edge placement error on dielectric wall are crucial. In addition, a tall & narrow-space active patterning is necessary in FS to enable dielectric wall and RMG patterning on dielectric wall. CFET enables ultimate CMOS scaling by N-P stacking architecture. However, the N-P stacking architecture creates process challenges. Monolithic CFET integration enables self-aligned active/gate/contact patterning. But it needs high aspect ratio patterning and vertical patterning for SD & contact, and RMG. Sequential CFET simplifies SD, RMG and contact integration by separating the process flow into top and bottom device [5]. But it needs wafer transfer without bonding defects, precise litho alignment between top and bottom processes and top-bottom gate connection. High aspect ratio via integration is a common challenge in monolithic and sequential CFET.

For more than two decades and through approximately ten technology nodes, the semiconductor industry has relied upon Dual Damascene copper interconnects. While there is vigorous debate as to the timing and dimensions of the transition, there is a general consensus that there will eventually be a need to replace copper with a different conductor metal. Motivations include copper’s requirement for space-consuming diffusion barriers and the contributions of interfacial electron scattering to higher resistance at smaller dimensions. Researchers such as D. Galla have proposed a range of candidate conductor metals, many of which would be patterned subtractively (by depositing blanket sheets of material and then etching away the portions not required for circuity). There is a growing body of literature considering the choice of metal, methods for controlling its morphology and electrical behavior, and processes for etching it. In this study, we examine a different facet of the transition from Damascene to subtractive conductor formation, specifically the role played by sidewall spacers in pattern formation and transfer. Because the dimensions at which non-Cu conductors may become competitive are well beyond the resolution limits of single exposure EUV, it is likely that an SADP process will be used. The common approach to pattern assembly for Damascene applications is to place mandrels where Cu conductors are ultimately desired, use ALD spacers on the mandrel sidewalls to define minimum-width dielectric spaces, then add a block pattern to define larger regions of dielectric and the remaining “non-mandrel” or “anti-mandrel” conductors. Then the mandrels are removed and the openings in the spacer+block mask are transferred into the dielectric, forming the trenches which will ultimately be filled with Cu. For subtractive metal patterning, preserving the existing circuit design and mask generating infrastructure favors a different approach: mandrels would still be placed at conductor locations and ALD spacers would still be used to define minimum dielectric spaces, but anti-mandrel conductor locations would be covered by new regions of masking material (rather than openings in the block mask). Then the spacers would be removed and the mandrels and anti-mandrel masks would be used to transfer the pattern into the metal below. This study focuses on comparison of the patterning performance of the two approaches using model structures to minimize the confounding impact of the subsequent etch steps (i.e., etching into ULK or metal). Topics of particular interest include LER, LWR, CDU, pitchwalking, and the effects of local variations in pattern density. Methods to improve patterning performance for both schemes will be discussed.

IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.

The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with a new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of the benefits in SGT is it can fully decouple the dependency of the gate length (Lg) and the source/drain (S/D) contact size from the contact gate pitch (CGP) scaling, which is seen as a hard limit for the conventional scaling. To fully realize the benefit of area gain and Lg scaling independent from lithography, the patterning challenges of 3D vertical device structure must be resolved. In this paper, we report the MOL patterning challenges in SGT device fabrication, such as Metal recess process, Bottom Contact formation (VBG), Cross point formation (XC), Top electrode (TE) patterning.