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13 June 2022 MOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)
Zheng Tao, Yisuo Li, Waikin Li, Minsoo Kim, Basoene Briggs, Katia Devriendt, Lieve Teugels, Farid Sebai, Christophe Lorant, Clement Porret, Erik Rosseel, Alfonso Sepúlveda Márquez, Nicolas Jourdan, Juergen Boemmels, Jerome Mitard, Philippe Matagne, Efrain Altamirano-Sánchez, Lars-ake Ragnarsson, Anish Dangol, Dmitry Batuk, Gerardo Tadeo Martinez Alanis, Jef Geypen, Kenichi Kanazawa, Testuo Izawa, Masakazu Kakumu, Koji Sakui, Nozomu Harada
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Proceedings Volume PC12056, Advanced Etch Technology and Process Integration for Nanopatterning XI; PC120560B (2022) https://doi.org/10.1117/12.2614772
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States
Abstract
The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with a new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of the benefits in SGT is it can fully decouple the dependency of the gate length (Lg) and the source/drain (S/D) contact size from the contact gate pitch (CGP) scaling, which is seen as a hard limit for the conventional scaling. To fully realize the benefit of area gain and Lg scaling independent from lithography, the patterning challenges of 3D vertical device structure must be resolved. In this paper, we report the MOL patterning challenges in SGT device fabrication, such as Metal recess process, Bottom Contact formation (VBG), Cross point formation (XC), Top electrode (TE) patterning.
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Zheng Tao, Yisuo Li, Waikin Li, Minsoo Kim, Basoene Briggs, Katia Devriendt, Lieve Teugels, Farid Sebai, Christophe Lorant, Clement Porret, Erik Rosseel, Alfonso Sepúlveda Márquez, Nicolas Jourdan, Juergen Boemmels, Jerome Mitard, Philippe Matagne, Efrain Altamirano-Sánchez, Lars-ake Ragnarsson, Anish Dangol, Dmitry Batuk, Gerardo Tadeo Martinez Alanis, Jef Geypen, Kenichi Kanazawa, Testuo Izawa, Masakazu Kakumu, Koji Sakui, and Nozomu Harada "MOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)", Proc. SPIE PC12056, Advanced Etch Technology and Process Integration for Nanopatterning XI, PC120560B (13 June 2022); https://doi.org/10.1117/12.2614772
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KEYWORDS
Optical lithography
Metals
Etching
Atomic layer deposition
Transistors
Electrodes
Inspection
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