Presentation
22 November 2023 Single exposure EUV process optimization for SNLP and BLP layer for next-generation DRAM manufacturing
Author Affiliations +
Abstract
In this paper, we share some early results on using EUV to pattern the Storage Node Landing Pad + Bit Line Peri. We use advanced processing techniques on the track, as well as advanced machine learning-based metrology to characterize the process. We have used a MOR to pattern the SNLP+BLP layer. In Figure 1 we show a SNLP+BLP design clip and the different sources which were optimized for the different pitches as well as a schematic of the process. Optimization with freeform sources was done to improve the pattern fidelity of these complex 2D patterns. In an attempt to improve CDU performance and reduce process variability, several approaches were investigated using SCREEN’s DT-3000 track. Amongst these approaches, a novel hotplate technology incorporating multi-zone temperature control was extensively explored during the PEB process, to deliver ultimate CD stability. SEM images acquired were denoised with advanced algorithms to better understand minute variations in pattern fidelity.
Conference Presentation
(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Andreia Santos, Jeonghoon Lee, Elke Caron, Syamashree Roy, Jelle Vandereyken, Masahiko Harumoto, Sandip Halder, Victor Blanco, Van Tuong Pham, and Bappaditya Dey "Single exposure EUV process optimization for SNLP and BLP layer for next-generation DRAM manufacturing", Proc. SPIE PC12750, International Conference on Extreme Ultraviolet Lithography 2023, PC1275004 (22 November 2023); https://doi.org/10.1117/12.2687539
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KEYWORDS
Extreme ultraviolet

Extreme ultraviolet lithography

Manufacturing

Defect detection

Error analysis

Photovoltaics

Scanning electron microscopy

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