This PDF file contains the editorial “Hot-Lot Equivalent of Technology Development—Immersion Lithography” for JM3 Vol. 3 Issue 02

This PDF file contains the editorial “Mask Technology for Optical Lithography” for JM3 Vol. 3 Issue 02

The multizone hotplate approach of the APB5500 bake system achieves temperature uniformity significantly superior to conventional bake tools, resulting in unmatched global critical dimension (CD) uniformity from the postexposure bake (PEB) process. Progress toward 65-nm next-generation lithography, however, requires the application of negative-tone chemically amplified resists (nCARs) like NEB22. This nCAR is characterized to show a strong sensitivity to postexposure delay (PED) in vacuum during electron-beam writing of 0.5 nm/h, and also a strong PEB sensitivity of 7.8 nm/°C, both resulting in systematic CD errors. These CD errors are compensated with the APB5500 bake system during PEB by automatically applying an appropriate nonuniform temperature profile. This temperature profile is calculated by an algorithm considering the resist and mask heat transfer properties. A CD uniformity improvement from 8.9 to 6.7 nm total range (≈25%) on a state of the art production mask is achieved.

Photomask dimensional metrology in the scanning electron microscope has not evolved as rapidly as the metrology of resists and integrated circuit features on wafers. This has been due partly to the 4× (or 5×) reduction in optical steppers and scanners used in the lithography process, and partly for the lesser need to account for the real three dimensionality of the mask structures. So, where photomasks are concerned, many of the issues challenging wafer dimensional metrology at 1× are reduced by a factor of 4 or 5 and thus could be temporarily swept aside. This is rapidly changing with the introduction of advanced masks with optical proximity correction and phase shifting features used in 100 nm and smaller circuit generations. Fortunately, photomask metrology generally benefits from the advances made for wafer metrology, but there are still unique issues to be solved in this form of dimensional metrology. It is likely that no single metrology method or tool will ever provide all necessary answers. As with other types of metrology, resolution, sensitivity and linearity in three-dimensional measurements of the shape of the lines and phase shifting features in general (width, height and wall angles) and departure from the desired shape (surface and edge roughness, etc.) are the key parameters. Different methods and tools differ in their capability to collect average and localized signals at acceptable speed, but in any case, application of thorough knowledge of the physics of the given metrology is essential to extract the information needed. This paper will discuss the precision, accuracy and traceability in SEM metrology of photomasks. Current and possible new techniques utilized in the measurements of photomasks including suppression of charge and highly accurate modeling for electron beam metrology will also be explored to answer the question, Has anything really changed?

Binary and phase-shifting chromium on quartz optical photomasks have been successfully investigated with high-pressure/environmental scanning electron microscopy (SEM). The successful application of this methodology to semiconductor photomask metrology is new because of the recent availability of high-pressure SEM instrumentation equipped with high-resolution, high-signal, field emission technology in conjunction with large chamber and sample transfer capabilities. The high-pressure SEM methodology employs a gaseous environment to help diminish the charge buildup that occurs under irradiation with the electron beam. Although very desirable for charge reduction, this methodology has not been employed in production photomask or wafer metrology until now. This is a new application of this technology to this area, and it shows great promise in the inspection, imaging and metrology of photomasks in a charge-free operational mode. This methodology also holds the potential of similar implications for wafer metrology. For accurate metrology, high-pressure SEM methodology also affords a path that minimizes, if not eliminates, the need for charge modeling. This paper presents some new results in high-pressure SEM metrology of photomasks.

To extend optical lithography technology to the sub-65-nm linewidth regime, all mask-related distortions must be eliminated or minimized. Thermal distortion during the exposure process can be a significant contribution to the total pattern placement error budget for advanced photomasks. Consequently, several finite element (FE) models were developed to predict the thermal and mechanical response of an optical reticle during exposure. We present the experimental verification of the FE thermal models. In particular, the results of the numerical simulation are compared with the experimental data and excellent agreement is found.

Today there is little practical experience with hard pellicles (HP), which is why we are doing a series of lithographic exposures of reticles with a HP on a 193-nm step-and-scan system at IMEC. The goal of this work is to experimentally verify the (optical) effects of HPs (such as their contribution to distortion and aberrations), find and perform suitable scanner corrections for them if possible, and then compare critical dimension (CD) measurements from exposures with HP to the corresponding exposures without HP. In this way, we can assess the viability of the use of hard pellicles in semiconductor industry. The result of our work so far is that we have found no show-stoppers for the use of HPs in lithography (although there are a few restrictions on this statement): most of the expected optical effects are confirmed experimentally and can-to a large extent-be corrected. The CD measurement part of the work yielded no unpleasant surprises: we basically find identical results with and without HP. There are, however, a few restrictions to this largely positive evaluation. The first is the fact that the specs on the pellicle flatness are currently not met (yet), which means that the contribution of the pellicle nonflatness to distortion is still larger than the 1-nm spec that is allowed for. However, progress in improving the impact of nonflatness is still ongoing, so the current status is by no means the final one. The second restriction is that none of the work we have done on our 193-nm system can give a clear indication to what extent possible oxygen purging or contamination issues may turn out to be troublesome once HPs are applied on a genuine 157-nm system. However, we plan to investigate such 157-nm specific topics soon, as a 157-nm scanner has been available at IMEC since the Fall of 2003.

We report in this work both experimental and theoretical results showing the effects of reticle absorber reflectivity on standard flare measurements, image formation, and how this may contribute to various image metrics used in lithography. Our study shows that under typical conditions the reflectance from the absorber film has only a small effect on the image produced by the exposure system and therefore should not limit lithography.

Three important concepts about the mask error enhancement factor (MEEF) are proposed. From the definition of MEEF, it could be derived as a function of the image log slope and the aerial image variation caused by mask critical dimension (CD) errors. Second, a mask error common window indicator (MECWIN) is proposed to evaluate the MEEF and mask CD specification by knowing the wafer CD tolerance. This concept is used to define the mask CD specification without any ambiguity. Finally, we describe the complex 2-D response to the mask-making error around the line end by a mask error enhancement tensor. Both theoretical derivations and experiments to justify the theory are presented.

The minimum gate pitch for the 65 nm device node will push 193 nm lithography toward k₁~0.35 with numerical aperture (NA)=0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65 nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift masks (high-T attPSMs), where T>14%, to improve process margins. The benefits of a high-T attPSM are substantial, but drawbacks like difficulty in inspection, defect free blank manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65 nm node with 193 nm lithography. Earlier work has shown that the problems high-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75 NA 193 nm wavelength results for 6% versus 9% attPSM on the gate, contact/via, and metal layers at 65 nm generation target dimensions with leading edge resists.

Focus monitor technology for attenuated phase shift masks under annular illumination has been developed for a in-line quality control. The focus monitor pattern on a reticle employs a pair of grouped lozenge-shaped opening patterns in the attenuated phase shifting region. Since the phase shifting angles of light passing through the first and second opening patterns are 90° and 0°, respectively, the best focus position for the first pattern shifts to that of the second pattern. Subtraction of the length of the patterns is a linear function of the actual focal position printed on the wafer. The linear function is insensitive to further mask phase error. Therefore, the effective focal position can be extracted by measuring that subtracted from the measured length. High resolution of 10 nm defocus was achieved using this technique.

In an optical vortex, the wavefront spirals like a corkscrew, rather than forming planes or spheres. Since any nonzero optical amplitude must have a well-defined phase, the axis of a vortex is always dark. Printed in negative resist at 248 nm and NA≥0.63, optical vortices and optical vortex arrays produce contact holes with 64 nmk₁<0.4), depending on exposure dose. Arrays of vortices with k_pitch>0.6 can be patterned using a chromeless phase-edge mask composed of rectangles with nominal phases of 0, 90, 180, and 270 deg. Lithography simulation and resist exposures have demonstrated process windows with ≈10%E_lat and ~400-nm depth of focus (DOF) for 85-nm CDs at 210-nm pitch with σ=0.15, but the developed contacts are somewhat elliptical. No significant surface development has appeared due to phase-edge printing. However, the spacewidth alternation phenomenon familiar from linear chromeless phase-edge lithography does cause small positional errors for vortex vias, and each of the four vortices in the repeating pattern may behave somewhat differently through focus, potentially limiting the common process window. Smaller CDs and pitches are possible with shorter wavelength and larger NA, while larger pitches give rise to larger CDs. At pitch >0.6 μm, the vortices begin to print independently for σ≥0.3. Such "independent" vortices have a quasi-isofocal dose that gives rise to 110-nm contacts with E_lat>14% and DOF >400 nm. In an actual chip design, unwanted vortices and phase step images would be erased from the resist pattern by exposing the wafer with a second, more conventional, bright-field trim mask. Compared to other ways of producing deep subwavelength contacts, the vortex via process reduces the lithography and process control challenges.

To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers are on their way to introduce the alternating phase shift mask (APSM) to be able to print the gate level on sub-130-nm devices. This is done at very high mask costs, long cycle times, and poor guarantees to get defect-free masks. Nakao et al. have proposed a new resolution enhancement technique (RET). They have shown that sub-0.1-μm features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension of this technique called complementary double exposure (CODE). It combines Nakao's technique and the use of assist features that are removed during a second subsequent exposure. This new method enables us to print isolated as well as dense features on advanced devices using two binary masks. We describe all the steps required to develop the CODE application. The layout rules generation and the impact of the second mask on the process latitude have been studied. Experimental verification has been done using 193-nm 0.63 and 0.75 numerical aperture (NA) scanners. The improvement brought by quadrupole or annular illuminations combined with CODE has also been evaluated. Finally, the results of the CODE technique, applied to a portion of a real circuit using all the developed rules, are shown.

Step and flash imprint lithography (S-FIL) is an attractive method for printing sub-100-nm geometries. Relative to other imprinting processes, S-FIL has the advantage of the template being transparent, thereby facilitating conventional overlay techniques. In addition, the imprint process is performed at low pressures and room temperature, minimizing magnification and distortion errors. As a result, it may be possible to use S-FIL to build integrated circuits. The purpose of this work is to investigate the fabrication methods needed to form templates capable of printing sub-100-nm contact holes. A positive resist process is used to image both holes and pillars on the template. After fabrication, the templates are used to print both contacts and pillars. The dense 80-nm imprinted contacts measure 65 nm, a consequence of undersizing on the template. For relaxed pitches, contacts smaller than 30 nm are observed. Pillars as small as 50 nm are also cleanly printed. At 40 nm, pillar size is inconsistent, and missing pillars are evident. Modifications to the template fabrication process will be necessary to study the feasibility of printing even smaller contacts and pillars.

For sub-100 nm integrated circuit (IC) technologies, many of the factors that affect the cost of photomasks, the cost of material, of the writing process, of the develop/etch process, and of inspection, are increasing by an order of magnitude per generation. In order to mitigate the impact of that increase on the return on investment of new IC products, mask shop deliverables such as yield or alignment with technology requirements need to reach new quality. This work focuses on cost containment of the mask by optimally utilizing existing reticle technology to meet device requirements at the product level. We first compare the increase of mask cost with that of other manufacturing equipment categories, and discuss their dependence on layer properties and how to control increasing costs. We then propose use of a new procedure called integrated simulation (optical combined with electrical) to estimate the impact of the mask critical dimension (CD) budget on transistor performance on the local scale (cell level) and global scale (die level). In the process, at the cell level, simulated aerial images of metal-oxide-semiconductor field-effect transistor channels are used to evaluate the parametric data dependence on the optical proximity effects and correction features at the mask grade assumed. At the die level, statistical distribution of device parameters in the die is derived to estimate the parametric yield impacted by mask CD variation. We also discuss how integrated simulation can help in resolving other challenges of advanced reticle manufacturing such as qualification of masks or the generation of dummy patterns.

Simulation studies along with the necessary experimental verification of the performance of a new combination bake-chill station designed by FSI International in its POLARIS^® thermal road-map project is presented in this paper. Since in this new design the 300-mm wafer is heated to the desired bake temperature and chilled back to room temperature before removed out of the station, a tight temperature control of the wafer throughout the process is achieved. To analyze the thermal performance of the station, an axi-symmetric model and a three-dimensional model geometrically similar to the new station are generated. The commercial CFD software Fluent^® is employed to solve the Navier Stokes and energy equations in the computational domain. Experimental data as measured by a 42-point OnWafer^TM temperature sensor wafer is used to verify the predictions of the simulated transient temperature behavior from the numerical model on the new station. Further, the simulations and experiments presented here substantiate the thermal agility of the proposed combination bake-chill station design. Higher throughput of the cluster, a major productivity improvement contribution of this new design, is also presented. Influence of the combination bake-chill station mechanical and thermal design losses on the wafer surface temperature uniformity and suggestions for improvements are also discussed.

A fabrication process has been developed which prevents solvent intermixing between layers of diazonaphthoquinone/novolac (DNQ/novolac) based resist. The process enables three-dimensional structures to be batch fabricated stereolithographically using integrated circuit-compatible resist, coating, and exposure techniques, followed by a single development step. To prevent solvent intermixing, a combination of solvent tailoring and surface treatment is employed. The photoresist is first constituted into a weaker, less polar solvent. Before coating a new layer, the surface is exposed to ozone, thus increasing the hydrophilicity of the surface and providing a less soluble barrier layer. This enables the formation of a stack of successively photoimaged layers of the same material, which are then developed in a single step. A new interlayer dose modulation technique to optimize the development process in positive tone resists such as DNQ/novolac is also described.

A microelectromechanical system electromagnetic optical scanner for horizontal scanning in a commercial laser scanning microscope has been developed. Major specifications include mirror size: 4.5×3.3 mm², resonant frequency: 4 kHz, changeable scan angle: 2.1-16°, mirror flatness: <244 nm, and scan angle stability: <0.1%. Initial development started with prototyping a scanner with polyimide hinge, but the stiffness and the Q-factor of polyimide hinge were found insufficient to realize the required resonant frequency and scan angle. On the other hand, a scanner with single crystal silicon hinge has been successfully developed. The electromagnetic scanner has an electroplated copper driving coil to reduce power consumption. A scanner controller using the output signal from an integrated sensing coil was also developed, and sufficient scan angle stability was obtained. The scanner has survived the life test of over 140 billion cycles. It has successfully satisfied all the specifications including not only the fundamentals such as resonant frequency and maximum scan angle but also the ones for commercial products such as scanning stability and durability. It has been commercialized as a part of our product OLS1100 (later remodeled as OLS1200).

We report on quartz and glass cutting by a lateral scanning of femtosecond pulses (150 fs at 1 kHz repetition rate) of 800 nm wavelength at room and low pressure (5 Torr) air ambience. Pulses were focused by a low numerical aperture (NA≤0.1) objective lens. Optimization of fabrication conditions: pulse energy and scanning speed were carried out to achieve large-scale (millimeter-to-centimeter) cutting free of microcracks of submicron dimensions along the edges and walls of the cut. Cutting through out the samples of 0.1-0.5 mm thickness was successfully achieved without apparent heat affected zone. At low air pressure (5 Torr) ambience, redeposition of ablated material was considerably reduced. It is demonstrated that the damage on the rear surface was induced by the stress waves, which originated from the plasma ablation pressure pulse. The mechanism of femtosecond-laser cutting of transparent materials at high irradiance and the influence of stress waves generated by plasma plume are discussed.