Mr. Akiyuki Sugiyama Profile

Akiyuki Sugiyama

at Hitachi High-Tech Corp

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Author

Publications (10)

Proceedings Article | 2 April 2014 Paper

Advanced CD-SEM metrology for pattern roughness and local placement of lamellar DSA

Takeshi Kato, Akiyuki Sugiyama, Kazuhiro Ueda, Hiroshi Yoshida, Shinji Miyazaki, Tomohiko Tsutsumi, JiHoon Kim, Yi Cao, Guanyang Lin

Proceedings Volume 9050, 90501T (2014) https://doi.org/10.1117/12.2060924

KEYWORDS: Semiconducting wafers, Line edge roughness, Line width roughness, Edge roughness, Etching, Critical dimension metrology, Finite element methods, Process control, Chemical analysis, Directed self assembly

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SPIE Journal Paper | 1 April 2011

Critical dimension scanning electron microscope local overlay measurement and its application for double patterning of complex shapes

Shoji Hotta, Takumichi Sutani, Scott Halle, Daniel Moore, Chas Archie, Akiyuki Sugiyama, Masahiko Ikeno, Atsuko Yamaguchi, Kazuyoshi Torii

JM3, Vol. 10, Issue 02, 023014, (April 2011) https://doi.org/10.1117/12.10.1117/1.3599867

KEYWORDS: Overlay metrology, Scanning electron microscopy, Double patterning technology, Electron microscopes, Data modeling, Semiconducting wafers, Optical lithography, Lithography, Error analysis, Wafer-level optics

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Proceedings Article | 2 April 2010 Paper

Spatial signature in local overlay measurements: what CD-SEM can tell us and optical measurements can not

Scott Halle, Daniel Moore, Chas Archie, Shoji Hotta, Takumichi Sutani, Akiyuki Sugiyama, Masahiko Ikeno, Atsuko Yamaguchi, Kazuyoshi Torii

Proceedings Volume 7638, 76381V (2010) https://doi.org/10.1117/12.846665

KEYWORDS: Overlay metrology, Double patterning technology, Scanning electron microscopy, Data modeling, Wafer-level optics, Optical testing, Lithography, Semiconducting wafers, Metrology, Visualization

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Proceedings Article | 2 April 2010 Paper

Concerning the influence of pattern symmetry on CD-SEM local overlay measurements for double patterning of complex shapes

Shoji Hotta, Takumichi Sutani, Akiyuki Sugiyama, Masahiko Ikeno, Atsuko Yamaguchi, Kazuyoshi Torii, Scott Halle, Daniel Moore, Chas Archie

Proceedings Volume 7638, 76381T (2010) https://doi.org/10.1117/12.846674

KEYWORDS: Overlay metrology, Double patterning technology, Scanning electron microscopy, Semiconducting wafers, Optical lithography, Control systems, Metrology, Lithography, Algorithm development, Detection and tracking algorithms

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Proceedings Article | 13 March 2009 Paper

High-precision contouring from SEM image in 32-nm lithography and beyond

Hiroyuki Shindo, Akiyuki Sugiyama, Hitoshi Komuro, Yutaka Hojo, Ryoichi Matsuoka, John Sturtevant, Thuy Do, Ir Kusnadi, Germain Fenger, Peter De Bisschop, Jeroen Van de Kerkhove

Proceedings Volume 7275, 72751F (2009) https://doi.org/10.1117/12.814430

KEYWORDS: Calibration, Optical proximity correction, Scanning electron microscopy, Line edge roughness, Edge detection, Algorithm development, Optical alignment, Semiconducting wafers, Data modeling, Critical dimension metrology

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Proceedings Article | 13 March 2009 Paper

Integration of mask and silicon metrology in DFM

Ryoichi Matsuoka, Hiroaki Mito, Akiyuki Sugiyama, Yasutaka Toyoda

Proceedings Volume 7275, 72751N (2009) https://doi.org/10.1117/12.816108

KEYWORDS: Photomasks, Silicon, Metrology, Optical proximity correction, Design for manufacturing, Semiconductors, Computer aided design, Lithography, Manufacturing, Edge detection

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We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Proceedings Article | 17 October 2008 Paper

New method of 2-dimensional metrology using mask contouring

Ryoichi Matsuoka, Yoshikazu Yamagata, Akiyuki Sugiyama, Yasutaka Toyoda

Proceedings Volume 7122, 71222T (2008) https://doi.org/10.1117/12.802137

KEYWORDS: Photomasks, Optical proximity correction, Metrology, Semiconductors, Edge detection, Computer aided design, Lithography, Profiling, Inspection, Design for manufacturing

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Proceedings Article | 30 October 2007 Paper

New method of contour-based mask-shape compiler

Ryoichi Matsuoka, Akiyuki Sugiyama, Akira Onizawa, Hidetoshi Sato, Yasutaka Toyoda

Proceedings Volume 6730, 67300M (2007) https://doi.org/10.1117/12.746559

KEYWORDS: Photomasks, Optical proximity correction, Edge detection, Computer aided design, Scanning electron microscopy, Profiling, Semiconductors, Design for manufacturing, Image processing, Data modeling

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Proceedings Article | 24 March 2006 Paper

Evaluation of OPC quality using automated edge placement error measurement with CD-SEM

Cyrus Tabery, Hidetoshi Morokuma, Akiyuki Sugiyama, Lorena Page

Proceedings Volume 6152, 61521F (2006) https://doi.org/10.1117/12.663017

KEYWORDS: Scanning electron microscopy, Optical proximity correction, Image processing, Image quality, Edge detection, Calibration, Metrology, Lithography, Process modeling, Image analysis

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Optical proximity correction (OPC) plays a vital role in the lithography process of cutting-edge IC fabrication. The quality of lithography models used in OPC is fundamental to the final performance of the OPC in production. Traditionally, two-dimensional proximity features such as line-end, bar-to-bar or bar-to-line were only partially characterized because of the difficulty in transferring the SEM information into the OPC model building process. A new methodology of edge placement error (EPE) measurement using CD-SEM is proposed as part of an OPC model building and process/OPC qualification flow. It is not easy to generate EPE measurements because of the inherent need to overlay the design and the SEM in order to quantify EPE. The quality of the EPE measurement depends on both the accuracy of the SEM image scan rotation and magnification, but also on the accuracy of pattern matching between the design layout pattern and the realized pattern (wafer). These problems do not exist in simulation, but model calibration requires a direct comparison between simulation and measurement. Measuring EPE effectively brings the measurement information into the realm of the design. Hitachi High-Technologies has developed a "fully automated EPE measurement function" based on design layout and detected edges of SEM image as a solution to this issue. This study shows several practical evaluation results using the automated EPE measurement function. The applications that will be discussed are as follows. 1) Design based classification of edges and subsequent quantification of SEM EPE for many types of edge arrangement and orientation. In this study, we will examine line-end-adjacent, line-end, corner, and other critical gate edges. 2) SEM image based classification of EPE fliers as a new population of errors. 3) Comparison between the detected edge of the feature within the SEM image and a polygon shape generated by lithography simulation to determine the quality of the simulation. 4) Conversion of the SEM image edge contour into an OASIS file and construction of a process variability band to quantify CD variability for all 2D contexts in a SEM image.

Proceedings Article | 10 May 2005 Paper

A new matching engine between design layout and SEM image of semiconductor device

Hidetoshi Morokuma, Akiyuki Sugiyama, Yasutaka Toyoda, Wataru Nagatomo, Takumichi Sutani, Ryoichi Matsuoka

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.602066

KEYWORDS: Scanning electron microscopy, Optical proximity correction, Semiconducting wafers, Image processing, Computer aided design, Edge detection, Image segmentation, Semiconductors, Metrology, Wafer testing

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Showing 5 of 10 publications

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