In the past few decades, leading edge logic technology scaling has been the main driver for semiconductor metrology developments. As traditional device scaling is slowing down, the semiconductor industry is focusing also on heterogeneous integration approaches, which leverage advanced packaging technologies to integrate devices designed and manufactured separately using the most suitable process technology for each device. Heterogeneous integration presents significant metrology challenges, which are different from what is encountered at the logic device level in terms of materials and specifically dimensions. Large-scale 3D structures need to be characterized with unprecedented accuracies and advanced optical techniques play a pivotal role. In this paper, some metrology challenges in heterogeneous integration are introduced and discussed related to TSV characterization including depth and reveal height, wafer bonding measurements, and dimensional and overlay metrology for processing leading to bump receivers and bump formation. Current capabilities utilizing various imaging and interferometry techniques are presented and their limitations discussed.
3-dimensional chiplet device architectures are expected to provide improved device performance, efficiency, and footprint beyond what is capable with 2-dimensional scaling technologies. Thick resist lithography of damascene and plating resists, as well as organic dielectric materials, plays a critical role in chiplet integration. However, thick resist lithography requires viscous resist solutions, specialized tooling, and long processing times. This makes patterning using these resists inherently prone to uniformity issues, which has become a crucial issue for scaling. This work highlights two strategic areas of thick resist patterning development: improved resist coating methods; and enhanced focus control during exposure. Herein, we show a track-based method for carefully controlled uniformity of the resist coating thickness, with some sacrifice of through-put. In addition, we show stepper-based focus methods to account for die level variations in resist and wafer thickness, as well as local topography. Combined, these provide precise cross-wafer control of thick resist dimensions.
As the industry continues to push the limits of integrated circuit fabrication, reliance on EUV lithography has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at Litho and Etch together with eliminating film-related defects.
These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns.
In particular improvements in the coater/developer hardware and process are required to enable the use of a wide variety of chemicals as well as compatibility with existing systems.
This paper reviews the ongoing progress in coater/developer processes that are required to enable EUV patterning sub-30nm line and space by using MOR (Metal Oxide Resist).
Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the second generation of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. A typical defect Pareto for EUV line-space patterning is dominated by bridging defects and pattern collapse. Regarding pattern collapse, careful attention needs to be paid to optimizing the rinse process to avoid the large forces that cause collapse during drying. In this paper, we present an optimized rinse technology that works to prevent that pattern collapse, especially on EUV line/space patterns below 40nm pitch. Additionally, this paper reviews the ongoing progress in track-based processes (coating, developer) that are required to enable EUV patterning. This work is especially focused on defect mitigation during film coating and resist developing processes, which have a direct effect on the occurrence of bridging defects during pattern transfer.
Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the second generation of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity improvements must be continued to meet patterning performance requirements. Tokyo Electron Limited (TELTM) and IBM Corporation are continuously developing manufacturing quality processes for EUV.
Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the full scaling entitlement of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity and LWR/LER must be improved in terms of patterning performance. Tokyo Electron Limited (TEL™) and IBM Corporation are continuously developing manufacturing quality processes for EUV. In this paper, we review the ongoing progress in coater/developer based processes (coating, developing, baking) that are required to enable EUV patterning.
Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL.
In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.
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