To meet the demanding requirements for pattern fidelity, critical dimension and placement errors on advanced masks, the use of multi-beam mask writers together with using low sensitivity resists became necessary and inevitable. To reach the targeted throughput on such low sensitivity resists, an increase of the beam current is necessary which results in two problems: worse beam stability control increases the risks of pattern errors and thus leads to higher yield loss. In addition, stronger resist charging and thermal effects also result in more unpredictable displacement errors which in turn make overlay control much more difficult. Here we present a new method that utilizes machine learning to detect tool abnormalities and trigger immediate exposure interruption which significantly reduces the mask yield loss. To reduce and compensate stronger charging and thermal effects from a higher beam current, we introduce hardware modifications and software corrections as well as an exposure sequence optimization that in combination minimize the yield loss and overlay problems and enable mask making in 3nm and beyond.
As wafer manufacturing shrinks size and pitch of features, and EUV lithography introduces high NA, the control of photomask pattern placement error that contributes to wafer overlay becomes a critical requirement for leading-edge devices. For sub-3nm node devices, the pattern complexity has increased and the exposure dose has also risen due to the use of low-sensitivity resist. Accordingly, to improve the pattern fidelity and reduce the exposure time, masks are manufactured using Multi-Beam Mask Writer (MBMW). As a result of analyzing the mask pattern placement error budget for the main EUV resist of sub-3nm node device, e-beam resist charging was found to be the most significant factor. This is primarily due to the inability to use a charging dissipation layer (CDL), caused by defect issues and degradation of critical dimension (CD) linearity. In this paper, we conduct an in-depth analysis of mask pattern placement errors induced by the charging effect in the MBMW and present a charging control methodology to mitigate these pattern-density-dependent errors. We test the charging effect reduction, an integrated solution of hardware and software for charging control in the MBMW, and showcase its performance for two resists. When applied to mass productions, the charging effect correction (CEC) significantly reduces mask pattern placement errors in a single cell and improves mask overlay between two critical layers aligned in an overlay alignment scheme. Ultimately, this leads to a reduction of wafer in-field overlay error.
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