Mr. Alexander Sauter Profile

Alexander Sauter

at Deutsches Zentrum für Luft- und Raumfahrt eV

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Publications (1)

Proceedings Article | 12 March 2024 Presentation + Paper

Physical layer forward error correction for free-space optical links

Oliver Griebel, Alexander Sauter, Uwe Wasenmüller, Lukas Steiner, Juraj Poliak, Balázs Matuz, Norbert Wehn

Proceedings Volume 12877, 128770J (2024) https://doi.org/10.1117/12.3001394

KEYWORDS: Matrices, Error control coding, Forward error correction, Free space optics, Energy efficiency, Satellites, Optical transmission, Design, Reliability

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We consider high data rate free-space optical links between satellite and ground station, which are prone to strong variations of the received signal due to atmospheric turbulence. The high data rates towards hundreds of Gbit/s paired with channel coherence times of a few milliseconds pose a serious challenge for reliable transmission. On such non-ergodic channels, the use of appropriate diversity techniques combined with channel coding schemes is a must to ensure the required data rates. There are several ways to tackle the problem. A pragmatic approach is to rely on commercial transceivers from fiber optics, which are, however, not tailored to the free-space optical channel. Code rates are high and no suitable diversity schemes are foreseen. Such transceivers can be combined with a suitable retransmission scheme, which strongly reduces spectral efficiency. Another option is the addition of a complementary erasure coding scheme at a higher layer, which, due to its long codewords and additional redundancy, can correct longer sequences of errors. However, such a layered scheme yields a loss in achievable data rates. In this work, we rely on a theoretically optimal approach which is composed of a long physical layer interleaver as well as a long physical layer channel code. While the interleaver should provide the required time diversity, the selected strongly quantized Low-Density Parity-Check (LDPC) code should correct the errors in the data. To support the required data rates, highly optimized hardware implementation becomes mandatory for both interleaver and decoder. To achieve high error correction performance and data rates towards hundreds of Gbit/s, a cross-layer design methodology is mandatory in which interleaver design, code, and decoding algorithms are jointly considered with its hardware implementation. We show that an Application-Specific Integrated Circuit (ASIC) implementation can reach the target data rates with a moderate backoff from theoretical limits.

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