Dr. Benjamin Szu-Min Lin Profile

Dr. Benjamin Szu-Min Lin

Lithography Application at Cymer Southeast Asia Ltd

SPIE Involvement:

Author

Publications (34)

Proceedings Article | 13 March 2012 Paper

Process requirements for pitch splitting LELE double patterning at advanced logic technology node

R. Peng, I. Huang, H. Liu, H. J. Lee, John Lin, Arthur Lin, Allen Chang, Benjamin Szu-Min Lin, Ivan Lalovic

Proceedings Volume 8326, 83260X (2012) https://doi.org/10.1117/12.916420

KEYWORDS: Double patterning technology, Critical dimension metrology, Etching, Lithography, Optical lithography, Photomasks, Photoresist materials, Logic, Optical simulations, Cadmium

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Proceedings Article | 4 March 2010 Paper

Laser spectrum requirements for tight CD control at advanced logic technology nodes

R. C. Peng, H. J. Lee, John Lin, Arthur Lin, Allen Chang, Benjamin Szu-Min Lin

Proceedings Volume 7640, 76402C (2010) https://doi.org/10.1117/12.846516

KEYWORDS: Critical dimension metrology, Optical lithography, Light sources, SRAF, Control systems, Logic, Logic devices, Laser applications, Reticles, Laser scanners

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Proceedings Article | 10 December 2009 Paper

High power LPP EUV source system development status

Benjamin Szu-Min Lin, David Brandt, Nigel Farrar

Proceedings Volume 7520, 752007 (2009) https://doi.org/10.1117/12.839488

KEYWORDS: Extreme ultraviolet, Tin, Extreme ultraviolet lithography, Reflectivity, Mirrors, Ions, Control systems, Lithography, Plasma, Coating

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Proceedings Article | 13 March 2009 Paper

Test structures for 40 nm design rule evaluation

Jonathan Ho, Yan Wang, Benjamin Lin

Proceedings Volume 7275, 72750T (2009) https://doi.org/10.1117/12.813448

KEYWORDS: Critical dimension metrology, Transistors, Lithography, Immersion lithography, Diffusion, Lens design, Design for manufacturability, Field programmable gate arrays, Design for manufacturing

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Proceedings Article | 4 December 2008 Paper

CD control enhancement by laser bandwidth stabilization for advanced lithography application

R. Peng, Tony Wu, K. W. Chang, C. P. Yeh, H. Liu, H. Lee, John Lin, Allen Chang, Benjamin Lin

Proceedings Volume 7140, 714041 (2008) https://doi.org/10.1117/12.804616

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Laser stabilization, Gas lasers, Signal processing, Beam controllers, Control systems, Laser applications, Lithography, Photoresist materials

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Proceedings Article | 4 December 2008 Paper

Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

M. C. Chiu, Benjamin Szu-Min Lin, M. F. Tsai, Y. S. Chang, M. H. Yeh, T. H. Ying, Chris Ngai, Jaklyn Jin, Stephen Yuen, Sem Huang, Yongmei Chen, Liyan Miao, Kevin Tai, Amiad Conley, Ian Liu

Proceedings Volume 7140, 714021 (2008) https://doi.org/10.1117/12.804685

KEYWORDS: Etching, Double patterning technology, Lithography, Optical lithography, Line width roughness, Manufacturing, Scanners, Semiconducting wafers, Line edge roughness, 193nm lithography

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High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.

Proceedings Article | 11 April 2008 Paper

The rapid introduction of immersion lithography for NAND flash: challenges and experience

Chan-Tsun Wu, Hung Ming Lin, Wei-Ming Wu, Meng-Hsun Chan, Benjamin Lin, Kuan-Heng Lin, Andrew Hazelton, Toshio Ohhashi, Katsushi Nakano, Yasuhiro Iriuchijima, Chunhsin Lee, Long Hung

Proceedings Volume 6924, 69241A (2008) https://doi.org/10.1117/12.772448

KEYWORDS: Photoresist materials, Semiconducting wafers, Particles, Scanners, Line width roughness, Immersion lithography, Lithography, Critical dimension metrology, Coating, Defect inspection

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Proceedings Article | 24 March 2008 Paper

Improve overlay control and scanner utilization through high order corrections

Hung Ming Lin, Benjamin Lin, James Wu, Smixer Chiu, Chin-Chou Kevin Huang, James Manka, Desmond Goh, Healthy Huang, David Tien

Proceedings Volume 6922, 69222R (2008) https://doi.org/10.1117/12.772118

KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Control systems, Manufacturing, Metrology, Data modeling, Process control, Semiconductors, Optical alignment

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Proceedings Article | 21 March 2007 Paper

A simple and practical approach for building lithography simulation models using a limited set of CD data and SEM pictures

Yan Wang, Jonathan Ho, Benjamin Lin, C.-L. Lin, Y.-C. Sheng, Yoyi Gong, Steven Hsu, Kechih Wu

Proceedings Volume 6521, 65211S (2007) https://doi.org/10.1117/12.712392

KEYWORDS: Data modeling, Calibration, Scanning electron microscopy, Critical dimension metrology, Lithography, Optical proximity correction, Cadmium, Semiconducting wafers, Process modeling, Optical calibration

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Proceedings Article | 29 March 2006 Paper

Process development and resist modification for metal trench layers from 65nm to 45nm nodes

Steven Wu, Sho-Shen Lee, Chun-Chi Yu, Benjamin Lin, Cheng Bai Xu, Yasuhiro Suzuki, Stewart Robertson, Tsutomu Tanaka, I-Yuan Wan

Proceedings Volume 6153, 615334 (2006) https://doi.org/10.1117/12.656640

KEYWORDS: Polymers, Thin film coatings, Lithography, Photoresist processing, Line edge roughness, Metals, Photomasks, Diffusion, Lithographic illumination, 193nm lithography

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Proceedings Article | 24 March 2006 Paper

Scatterometry measurements of line end shortening structures for focus-exposure monitoring

Kelvin Hung, Yung Feng Cheng, Jie Wei Sun, Benjamin Szu-Min Lin, Steven Fu, Thaddeus Dziura, Marcelo Cusacovich, Walter Mieher

Proceedings Volume 6152, 61521W (2006) https://doi.org/10.1117/12.655746

KEYWORDS: Single crystal X-ray diffraction, Semiconducting wafers, Data modeling, Scatterometry, Finite element methods, Lithography, Metrology, Process control, Photoresist processing, Scatter measurement

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Proceedings Article | 21 March 2006 Paper

Inverse lithography technology at chip scale

Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Proceedings Volume 6154, 615414 (2006) https://doi.org/10.1117/12.656827

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, Scanning electron microscopy, Calibration, Image quality, Semiconducting wafers, Image processing, Semiconductors

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Proceedings Article | 14 March 2006 Paper

Full-chip lithography manufacturability check for yield improvement

Yongfa Huang, Edward Tseng, Benjamin Szu-Min Lin, Chun Chi Yu, Chien-Ming Wang, Hua-Yu Liu

Proceedings Volume 6156, 61560W (2006) https://doi.org/10.1117/12.656401

KEYWORDS: Process modeling, Finite element methods, Semiconducting wafers, Data modeling, Photomasks, Lithography, Manufacturing, Calibration, Photoresist processing, Inspection

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Proceedings Article | 14 March 2006 Paper

DFM: a practical layout optimization procedure for the improved process window for an existing 90-nm product

Jonathan Ho, Yan Wang, Ya-Ching Hou, Benjamin Szu-Min Lin, Chun Chi Yu, Kechih Wu, Cliff Ma

Proceedings Volume 6156, 61560C (2006) https://doi.org/10.1117/12.656085

KEYWORDS: Design for manufacturing, Optics manufacturing, Optical simulations, Optical proximity correction, Critical dimension metrology, Field programmable gate arrays, Metals, Scanning electron microscopy, Diffraction, Microelectronics

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Proceedings Article | 9 November 2005 Paper

FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Jonathan Ho, Xin Wu, Petrisor Panaite, Manoj Chacko, Yunqiang Zhang, Wen-Kang Lei

Proceedings Volume 5992, 59925A (2005) https://doi.org/10.1117/12.637426

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Critical dimension metrology, Design for manufacturing, Halftones, Manufacturing, Semiconducting wafers, Image processing, Field programmable gate arrays

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Proceedings Article | 5 November 2005 Paper

Real-world impacts of inverse lithography technology

Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Proceedings Volume 5992, 59921Z (2005) https://doi.org/10.1117/12.632211

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, Scanning electron microscopy, Calibration, Image quality, Semiconducting wafers, Semiconductors, Image segmentation

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Proceedings Article | 17 May 2005 Paper

Optimization of multi-step development scheme to improve the critical dimension uniformity

Hsien-an Chang, Benjamin Szu-Min Lin, Kuei-Chun Hung, Shu-Ping Fang, Te-shao Hsu

Proceedings Volume 5755, (2005) https://doi.org/10.1117/12.599321

KEYWORDS: Deep ultraviolet, Critical dimension metrology, Annealing, Oxides, Double patterning technology, Integrated circuits, Chemical reactions, Process control, Astatine, Microelectronics

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Tight control of critical dimensions (CDs) of integrated circuit (IC) is required to achieve desired circuit performances, and getting more and more important as the IC CD shrinks. Phenomena and solutions of inter-field and intra-field CD errors have been widely studied for years. One of the well-known intra-field CD errors is so called the developer micro-loading effect due to the different pattern density loadings across the exposure field, in the other words, the more different the pattern density is, the more CD errors it would be expected. Some of the circuit layouts, e.g. thick gate oxide layers of dual gate oxide processes, and gate layers of embedded memory products, have this kind of across field pattern density concerns because of the different pattern density areas. Some researches showed that eliminating the by-products during the development process could reduce the developer micro-loading effect. With a multi-step development process (Puddle-Static Development-Dry-Puddle-Static Development-Rinse/Dry), the by-products can be removed and achieve a better CD uniformity. In this paper, optimization of the first puddle time in the multi-step development process is found to be the most critical to achieve uniform intra-field CDs. The purpose of the first puddle step is not only to remove the by-products but also to control the influence of the by-products to achieve uniform intra-field CDs. Once most of the by-products generated during the whole development process were carried away by the first puddle step, the optimum static Dev. time is needed to obtain the minimum intra-field CD difference. However, different photo-resists with different chemical formulations are expected to have identical optimum puddle time due to different chemical reactions of each by-product species, e.g. i-line PRs vs DUV PRs, or annealing type DUV PRs vs acetel type DUV PRs. These comparisons will be explained in details in this paper. Finally, the source of the by-products during the developer process was also identified to verify the validation of the multi-step developer process.

Proceedings Article | 17 May 2005 Paper

Feasibility of improving CD-SEM-based APC system for exposure tool by spectroscopic-ellipsometry-based APC system

Wen-Kuang Lin, Shih-Hsien Liao, Ronghao Tsai, Mike Yeh, Calvino Hsieh, Y. Yu, Benjamin Szu-Min Lin, Steven Fu, Thaddeus Dziura

Proceedings Volume 5755, (2005) https://doi.org/10.1117/12.598983

KEYWORDS: Critical dimension metrology, Single crystal X-ray diffraction, Etching, Scanners, Metrology, Process control, Spectroscopy, Control systems, Switching, Spectroscopic ellipsometry

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Lot-to-lot ADI CD data are generally used to tighten the variation of exposure energy of an exposure tool through an APC feedback system. With decreasing device size, the process window of an exposure tool becomes smaller and smaller. Therefore, whether the ADI CD can reveal the real behavior of a scanner or not becomes more and more a critical question, especially for the polysilicon gate layer. CD-SEM has generally been chosen as the metrology tool for this purpose. Because of the limitations of top-down CD-SEMs, an APC system could be easily misled by improper ADI CD data if the CD data were measured on a T-topped photo resist. ArF resist shrinkage and line edge roughness are also traditional causes for improper CD feedback if the user did not operate the CDSEM carefully. Another candidate for this APC application is spectroscopic-ellipsometry-based scatterometry technology, commonly referred to as SpectraCD. In recent studies, SpectraCD was proven to be able to reveal profile variation with excellent stability. The feasibility of improving a CDSEM-based APC system by a SpectraCD-based system in a high-volume manufacturing fab is therefore worthy of study. This study starts from an analysis of the historical data for the polysilicon ADI CD of a 130 nm product. Two different sets of CD measured from the two different metrology tools were analyzed. In the fab, CDSEM was the metrology tool chosen for the APC feedback. The CD data measured by SpectraCD over a 2 month timeframe were plotted as a CD trend chart of the specific exposure tool. There are several trend-ups and trend-downs observed, even though the overall CD range is small. After a series of analyses, the exposure tool has been proven to be quite stable and the CD data measured by SpectraCD also reveal the real behavior of the exposure tool correctly. The scanner is shown to have been misled by improper CD feedback. In comparison with CDSEM, the linearity of the correlation between ADI and AEI CDs, which represents the consistence of etch bias, can also be improved from 0.4 to 0.8 by SpectraCD. The root causes are still under investigation, but one suspected reason is related to resist profile. All the analysis results will be reported in this paper. The data provided sufficient motivation for switching the APC feedback system of the fab from a CDSEM-based system to a SpectraCD-based system. The results of the new APC system will also be discussed.

Proceedings Article | 12 May 2005 Paper

Optimization of multi-pole aperture for via patterning of 90 nm logic devices by KrF lithography

Shu Fang, Hsiang Yang, Hsien-an Chang, Paul Chiang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598707

KEYWORDS: Lithography, Photomasks, Lithographic illumination, Optical lithography, Logic devices, Optical resolution, Photoresist materials, Manufacturing, Printing, Airborne remote sensing

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Proceedings Article | 12 May 2005 Paper

Feasibility study of sub-65nm contact/hole patterning

Yung Cheng, Te Wu, C. Lin, Sheng Chang, Benjamin Lin

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.599571

KEYWORDS: Lithographic illumination, Optical lithography, Lithography, Logic, Optical proximity correction, Photomasks, Resolution enhancement technologies, Printing, Manufacturing, SRAF

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Proceedings Article | 10 May 2005 Paper

Reaching a CD uniformity of below 3 nm for 300 mm post-etch wafers by adjusting the CD distribution of ADI wafers

Jie-Wei Sun, Yong-Fa Huang, Sho-Shen Lee, Chun-Chi Yu, Benjamin Lin, Steven Fu, Mike Slessor

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598979

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Etching, Metrology, Single crystal X-ray diffraction, Lithography, Spectroscopic ellipsometry, Inspection, Scatterometry, Temperature metrology

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Proceedings Article | 10 May 2005 Paper

The performances of different overlay mark types at 65nm node on 300-mm wafers

H. Tseng, Ling-Chieh Lin, I. Huang, Benjamin Lin, Chin-Chou Huang, Chien-Jen Huang

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598424

KEYWORDS: Overlay metrology, Chemical mechanical planarization, Metrology, Semiconducting wafers, Tungsten, Optical alignment, Manufacturing, Metals, Image processing, Optical design

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The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations. Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.

Proceedings Article | 5 May 2005 Paper

DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Henry Lin, Manoj Chacko, Xiaoyang Li, Wen-Kang Lei, Jonathan Ho, Xin Wu

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.598838

KEYWORDS: Photomasks, Design for manufacturing, Optical proximity correction, Critical dimension metrology, Image processing, Manufacturing, Electronic design automation, Etching, Halftones, Lithography

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Proceedings Article | 4 May 2005 Paper

Global planarization of gap-filling process for low-k dual damascene applications

Ruei Hung Hsu, I. Huang, Ling Chieh Lin, Benjamin Szu-Min Lin

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.600408

KEYWORDS: Coating, Etching, Semiconducting wafers, Lithography, Photoresist materials, Optics manufacturing, Optical lithography, Copper, Scanning electron microscopy, Critical dimension metrology

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Proceedings Article | 6 December 2004 Paper

Double dipole lithography for 65-nm node and beyond: defect sensitivity characterization and reticle inspection

Stephen Hsu, Tsann-bin Chu, Douglas Van Den Broeke, J. Fung Chen, Michael Hsu, Noel Corcoran, William Volk, Wayne Ruch, Jean-Paul Sier, Carl Hess, Benjamin Lin, Chun-Chi Yu, George Huang

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569367

KEYWORDS: Inspection, Reticles, Photomasks, Lithography, Resolution enhancement technologies, Defect inspection, Semiconducting wafers, Model-based design, Optical proximity correction, Scattering

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Proceedings Article | 28 May 2004 Paper

Extension of ArF lithography for poly gate patterning of 65nm generation and beyond

Shu-Hao Hsu, Shu-Ping Fang, I. Hsuing Huang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.534641

KEYWORDS: 193nm lithography, Lithography, Line edge roughness, Optical lithography, Chromium, Coherence (optics), Image processing, Resolution enhancement technologies, Photoresist materials, Optical proximity correction

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Proceedings Article | 28 May 2004 Paper

Specification of the phase angle of a 6% attenuated PSM mask used in ArF lithography

Ching-Hsu Chang, Jochen Schacht, Benjamin Lin, Kuei-Chun Hung, I. Hsuing Huang

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535167

KEYWORDS: Critical dimension metrology, Photomasks, Image transmission, Reticles, Lithography, Phase shifts, Scanning electron microscopy, Binary data, Monochromatic aberrations, Transmittance

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Proceedings Article | 28 May 2004 Paper

Calibration of OPC models for multiple focus conditions

Jochen Schacht, Klaus Herold, Rainer Zimmermann, J. Andres Torres, Wilhelm Maurer, Yuri Granik, Ching-Hsu Chang, G. Kuei-Chun Hung, Benjamin Szu-Min Lin

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.534123

KEYWORDS: Calibration, Data modeling, Process modeling, Optical proximity correction, Photoresist processing, Image processing, Metrology, Thin films, Image acquisition, Error analysis

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Proceedings Article | 24 May 2004 Paper

Capability of spectroscopic ellipsometry-based profile metrology for detecting the profile excursion of polysilicon gate

Mike Yeh, Shu-Ping Fang, Bo-Jau Tsau, Chih-Chung Huang, Benjamin Lin, Steven Fu, Jay Chen, Regina Freed, Ted Dziura, Mike Slessor

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536269

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Metrology, Etching, Spectroscopic ellipsometry, Cadmium, Scanning electron microscopy, Transistors, Atomic force microscopy, Single crystal X-ray diffraction

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Proceedings Article | 29 April 2004 Paper

Improvement of 90nm KrF Cu process window by minimizing via deformation caused by low-frequency resonance of scanner projection lens

Shu-Ping Fang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.535046

KEYWORDS: Lithography, Scanners, Back end of line, Copper, Optical proximity correction, Semiconducting wafers, Manufacturing, Photomasks, Inspection, Critical dimension metrology

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Proceedings Article | 17 December 2003 Paper

Implementing AAPSM in 90-nm product with practical image imbalance correction

Benjamin Lin, Shu-hao Hsu, I. H. Huang, Kunyuan Chen, Frank Hsieh, Tony Hsu, Hua-Yu Liu, Armen Kroyan, Freeman Hsu, Jason Huang

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518029

KEYWORDS: Photomasks, Semiconducting wafers, Quartz, Optical proximity correction, Binary data, Phase shifts, Reticles, Neodymium, Optical lithography, Manufacturing

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Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.

Proceedings Article | 28 August 2003 Paper

Practical approach for AAPSM image imbalance correction for sub-100-nm lithography

Hung Lin Cho, Shu Yi Lin, Frank Hsieh, Armen Kroyan, Hua-Yu Liu, Jason Huang, Shu-Hao Hsu, I-Hsiung Huang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504393

KEYWORDS: Photomasks, Chromium, Critical dimension metrology, Manufacturing, Lithography, Semiconducting wafers, Reticles, Scanning electron microscopy, Optical proximity correction, Image resolution

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Proceedings Article | 24 July 2002 Paper

Challenges of 50-nm gate process in alternating phase shifting lithography

Cheng Fang, Kuei-Chun Hung, Z. Huang, Benjamin Lin, Shu-Hao Hsu, Yeong-Song Yen, Paul Yen, Jiunn-Ren Huang, Hua-Yu Liu

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474238

KEYWORDS: Critical dimension metrology, Lithography, Photomasks, Diffusion, Phase shifts, Optical proximity correction, Photoresist materials, Phase shifting, Binary data, Optical lithography

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Proceedings Article | 5 July 2000 Paper

Comparison between 2-phase-shifting mask and 3-phase-shifting mask on application of printing low-duty-ratio contact array patterning

Kuei-Chun Hung, Benjamin Lin, Hsien-an Chang, Alex Tseng, Lien-Sheng Chung, WeiJyh Liu, Der-Yuan Wu, Peter Huang

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388974

KEYWORDS: Distortion, Printing, Optical lithography, Photomasks, Scattering, Etching, Phase shifts, Critical dimension metrology, Photoresist materials, Scanning electron microscopy

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Showing 5 of 34 publications

Conference Committee Involvement (3)

SPIE Lithography Asia - Korea

13 October 2010 | n/a, Republic of Korea

SPIE Lithography Asia - Taiwan

18 November 2009 | Taipei, Taiwan

SPIE Lithography Asia - Taiwan

4 November 2008 | Taipei, Taiwan

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