The use of a physical guard ring in CMOS single-photon avalanche diodes (SPADs) based on n + /(deep)p-well and p + /(deep)n-well structures is a common solution to control the electric field of the SPADs periphery and prevent the premature lateral breakdown. However, this leads to a decrease of the detection efficiency, i.e., the fill-factor, especially when the SPADs size is reduced. Our paper presents an experimental and simulation study on replacing the physical guard ring by a virtual guard ring to improve the fill-factor and the scalability of a n + / p-well SPAD implemented in 0.35-μm pin-photodiode CMOS technology. Accordingly, the optimization of the virtual guard ring and its superiority at downscaling are discussed, and the SPAD scalability in size with respect to the fill-factor is quantified in this technology.
A monolithic optical receiver containing four single-photon avalanche diodes (SPADs) fabricated in 0.35-μm high-voltage (HV) CMOS is introduced and compared with two 4-SPAD receivers realized in pin-photodiode CMOS belonging to the same process family. This HV-CMOS SPAD receiver achieves sensitivities of −55.1 dBm at 50 Mbit / s and −52.0 dBm at 100 Mbit / s, both with digital processing, a bit error rate (BER) of 2 × 10 − 3, and return-to-zero coding using a wavelength of 642 nm. Also at 143 Mbit / s, this BER is achievable. This receiver is especially interesting for applications in which low light intensities can be expected, such as quantum key distribution, optical communications from deep space, and visible light communication for short-range consumer applications.
We investigate single-photon avalanche diodes with a thick absorption zone leading to a high photon detection probability in the near-infrared spectrum, e.g., to 27.9% at 850 nm. Furthermore, modulation doping for tuning the breakdown voltage in single-photon avalanche diodes is used. Modulation doping allows for reduction of the effective doping in the structure during the design phase without process modifications. We compare a modulation doped version with a single-photon avalanche diode not using this technique. We prove that both versions are operational. The modulation doped version shows a reduced dark count rate and afterpulsing probability at the cost of a reduced photon detection probability.
A fully integrated single-photon avalanche diode (SPAD) using a high-voltage quenching circuit fabricated in a 0.35-μm CMOS process is proposed. The quenching circuit features a quenching voltage of 9.9 V, which is three times the nominal supply voltage to increase the photon detection probability (PDP). To prove the quenching performance, the circuit has been integrated together with a large-area SPAD having an active diameter of 90 μm. Experimental verification shows a maximum PDP of 67.8% at 9.9 V excess bias at a wavelength of 642 nm.
Optimizing avalanche photodiodes (APDs) in standard complementary metal–oxide–semiconductor (CMOS) processes is challenging due to fixed doping concentrations of the available wells. A speed-improved APD in pin photodiode CMOS technology for high-sensitivity and high-speed applications using a lateral well modulation-doping technique is presented. The increased operating voltage of the presented device leads to a −3-dB bandwidth of 2.30 GHz with a multiplication factor of 20 for 1-μW optical power. This corresponds to a responsivity of 7.40 A/W. A multiplication factor of 44,500 was measured at 10-nW optical power. The thick absorption zone leads to an unamplified quantum efficiency of 72.2% at 635-nm wavelength.
We present the first optoelectronic integrated bipolar complementary metal oxide semiconductor (BiCMOS) receiver chip with an avalanche photodiode (APD). A large 200-μm-diameter APD connected to a high-speed transimpedance amplifier designed for a 2-Gbps optical wireless communication system is proposed. The complete chip was realized in a 0.35-μm silicon BiCMOS technology. Due to the thick intrinsic zone and multiplication gain, the responsivity of the APD reaches a value of up to 120 A/W for a wavelength of 675 nm. Furthermore, the capacitance of the APD is <500 fF for reverse bias voltages above 18 V. The receiver has a supply voltage of 3.3 V with a current consumption of 76 mA. The delivered 50-Ω single-ended output swing is 550 mVpp and the overall transimpedance is 260 kΩ with 1.02-GHz bandwidth. The achieved data rate is 2 Gbps with a sensitivity of −30.3 dBm at a bit error rate <10−9.
An avalanche photodiode (APD) fabricated in 0.35 μm high-voltage complementary metal-oxide semiconductor (CMOS) technology, which was originally optimized for linear mode applications, is characterized in Geiger mode operation. This work shows that the used design concept is also suitable for single-photon detection applications and achieves a photon detection efficiency of 22.1% at 785 nm due to a thick detection zone and 3.5 V excess bias. At this operation point, the single-photon APD achieves good results regarding afterpulsing probability (3.4%) and dark count rate (46 kHz) with respect to the large active diameter of 86 μm.
A pn-junction photodiode with a bandwidth in the GHz range is presented. This photodiode is fabricated in a standard 0.35‐μm high-voltage CMOS process with deep n-wells which can isolate negative substrate potentials down to −100 V from the MOS transistors. This photodiode can, therefore, be implemented together with circuits on the same chip. At a reverse bias voltage of −90 V, a bandwidth of 1.2 GHz was measured for 670-nm light. The breakdown voltage of this photodiode is about −180 V.
The presented linear mode avalanche photodiode (APD) uses the standard layers and process steps available in the 0.35-μ m Si bulk CMOS process. Due to a low-doped epitaxial layer with a resistivity of 664 Ω cm , a deep intrinsic zone is realized to enable a large depleted absorption region at already moderate bias voltages and therefore ensures a high low-voltage responsivity. In combination with avalanche gain at high bias voltages, this leads to an overall responsivity of 1.7×10 5 A/W at 1.1 nW optical input power and 670-nm wavelength. The maximum achieved avalanche gain was 4.94×10 5 . The maximum −3 dB frequency of 700 MHz was measured at a reverse bias voltage of 30 V and an optical input power of 14.7 μ W.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.