According to the Power-Performance-Area requirements in advanced technology node, we already scaled down poly pitch (CPP) and metal pitch (MP) which considered as main factors to form standard cell (SDC) area. However, in recent technology nodes, the scaling of CPP and MP started to slow down, due to the physical limitation. To continue to meet the requirements, combined with Design-Technology co-optimization (DTCO), the height of standard cell would become the main factor here, which we could reduce it by reducing the number of tracks. In this paper, we would introduce 3DIC as one of the design options for 2nm node to keep scaling by reducing the cell height with its specific 3D structure and inserted booster. Also, we would introduce the coming challenges as importing 3D-IC to 2nm technology node.
As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.
KEYWORDS: Back end of line, Standards development, Metals, Field effect transistors, Multiplexers, Logic, Fin field effect transistors, Dielectrics, Control systems, Clocks
Due to a slowdown in gate pitch scaling linked to fundamental physical limitation, standard cell height reduction is needed to achieve the scaling targets. The complementary FET consisting of stacked NMOS on PMOS device is evaluated for both monolithic and sequential integration. Due to double MOL level access, both CFET options combined with buried power rails reduce the standard cell track height down to 4T, also reducing the routing layer usage within the standard cell. The main advantages of sequential CFET over monolithic is the independent optimization of the top and bottom devices, and the possibility of split gate implementation which offers an area gain in complex cells such as flops, at the expenses of higher cost and process complexity.
CMOS technology scaling is enabled by multiple logic transistor architecture change from Planner to FinFET to Nanosheet and most recently Forksheet and CFET. Every architecture change has significant impact on the power-performance-area (PPA) scaling of any system on chip (SOC). A comprehensive Design-Technology-optimization (DTCO) methodology is needed to analyze this impact. In this paper technology scaling impact of this architecture change along with lithographic scaling will be analyzed from standard Cell to Block Level Place-Route to realize realistic PPA estimate.
KEYWORDS: Standards development, Metals, 3D imaging standards, Logic, System on a chip, Back end of line, Semiconducting wafers, Optical lithography, Wafer bonding, Fin field effect transistors
As traditional pitch scaling is losing steam, 3D logic is being explored to further extend density scaling as an alternative to continued standard cell scaling. This paper will discuss standard cell architectures to be used in a Sequential 3D process where the SoC is comprised out of 2 or more tiers of active CMOS with a given BEOL metal stack per tier. Using backside interconnect metals as standard cell power rails, a smart partitioning of the metal usage within standard cells can be obtained leading to 4 track cell height scaling. A design abstraction using crenelated design is however needed at block level to mitigate via and metal line end conflicts.
N2 node is introduced at 42nm poly pitch (CPP), 16 metal pitch (MP) by using 5 tracks (5T) cell height, single fin, and buried power rail (BPR). Due to the extreme cell height reduction, the patterning of the middle of line (MOL) become challenging. In this paper, two contact patterning schemes, staggered and aligned are presented and evaluated in terms of their impact on electrical performance on FinFET and Nanosheet. Simulations show that both options meet the performance target for N2. However, scaling at these dimensions also challenges the p-n separation between devices in a logic cell, which results in area penalty in complex cells. A novel device is introduced at N2 node, Forksheet, which shows higher performance and better area scaling at standard cell level compared to FinFET and NanoSheet.
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