EUV (Extreme Ultraviolet) Lithography has been delayed caused by several technical problems such as
EUV mask, source power and etc. So ArF immersion lithography has been continued with adopting new
technology. Especially, the wafer lithography tends to increase rapidly NTD(Negative Tone Develop) process
for overcoming high resolution such as small hole type patterns. For wafer NTD process, the pattern shape in
mask has changed from hole pattern to dot pattern. Also the local CD uniformity of aerial image is getting
more important. In this paper, we studied local CD uniformity with analyzing aerial images of high
transmittance HT-PSM (attenuated phase-shift mask) and conventional 6% HT-PSM from AIMS (Aerial Image
Measurement System) tool. Additionally, several cell sizes were analyzed to find an optimum target cell size
which has good wafer performance and AIMS aerial image. And we analyzed NILS(Normalized Image Log
Slope) factor which represent wafer photolithographic performance. Furthermore, we analyzed not only AIMS
NILS simulation, but also wafer lithographic performance.
One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography.
In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirk's disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which
will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around
40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is
going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF
immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been
examined intensively. However, double patterning and spacer patterning technology are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore,
lithography community is looking forward to improving maturity of EUVL technology.
In order to overcome several issues on EUV technology, many studies are needed for device application. EUV
technology is different characteristics with conventional optical lithography which are non-telecentricity and mask
topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of
oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern
direction, pattern type and slit position of target pattern.1
For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase
Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive
maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are
performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM
cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with
contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment.
Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are
also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated
shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is
around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with
line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical
absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch.
Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the
case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best
performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern
because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning
performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.
As the semiconductor feature size continues to shrink, electrical resistance issue is becoming one of the
industry's dreaded problems. In order to overcome such problem, many of the top semiconductor manufacturers have
turned there interest to copper process. Widely known, copper process is the trench first damascene process which
utilize dark tone mask instead of widely used clear tone mask. Due to unfamiliarity and under development of dark tone
mask technology compared to clear tone mask, many have reported patterning defect issues using dark tone mask.
Therefore, necessity of DFM[1] for design that meets both dark and clear tone is very large in development of copper
process based device.
In this study, we will propose a process friendly Design For Manufacturing (DFM) rule for dual tone mask.
Proposed method guides the layout rule to give same performance from both dark tone and clear tone mask from same
design layout. Our proposed method will be analyzed on photolithography process margin factors such as Depth Of
Focus (DOF) and Exposure Latitude (EL) on sub 50nm Flash memory interconnection layer.
As the semiconductor industry continues progressing toward increasingly complex and
unforgiving processes of device shrinkage and shorter duration of device development, many
industry participants from photo-lithography are taking interest in material and structure of the
photolithography mask. Due to shorter wavelength of the source laser and device technology
ranging around the order of magnitude for the source laser wavelength (ArF), the difference in mask
material and structure shows greater performance difference then larger technology node. Especially
around 50nm and beyond, many industry followers are reporting better performance from different
types of mask then previously used.
In this study, we will analyze the effect of the photo lithography mask material for sub
50nm device, in development perspective. Two major types of mask will be evaluated on the scale
of device development. Effects such as Mask Error Effect Factor (MEEF), Depth of Focus (DOF),
Exposure Latitude (EL) and Critical Dimension Uniformity (CDU) will be analyzed for both binary
and attenuated phase shifted mask under different process condition. Also, we will evaluate the
comparison result for application on development of sub 45nm device.
An epidemic for smaller node has been that, as the device architecture shrinks, lithography process requires
high Numerical Aperture (NA), and extreme illumination system. This, in turn, creates many lithography problems such
as low lithography process margin (Depth of Focus, Exposure Latitude), unstable Critical Dimension (CD) uniformity
and restricted guideline for device design rule and so on. Especially for high NA, extreme illumination such as
immersion illumination systems, above all the related problems, restricted design rule due to forbidden pitch is critical
and crucial issue. This forbidden pitch is composed of numerous optical effects but majority of these forbidden pitch
compose of photo resist residue and these residue must be removed to relieve some room for already tight design rule.
In this study, we propose automated algorithm to remove photo resist residue due to high NA and extreme
illumination condition. This algorithm automatically self assembles assist patterns based on the original design layout,
therefore insuring the safety and simplicity of the generated assist pattern to the original design and removes any resist
residue created by extreme illumination condition. Also we tested our automated algorithm on full chip FLASH
memory device and showed the residue removal effect by using commercial verification tools as well as on actual test
wafer.
As the design rule shrinks to its natural limit, reduction in lithography process margin and high Critical
Dimension (CD) error gives rise to use of many Resolution Enhancement Techniques (RET). Recently, one the popular
RET method to solve the above problem is polarized illumination. It is used to enhance the reduced lithography process
margin and enhance CD uniformity. Polarization lithography basically uses one sided polarized light source. Therefore
process margin increases for smaller design rule patterns. In this paper, we will present the results for polarized
illumination based Optical proximity Correction (OPC) for sub-60nm memory device. First, models for polarization
based and un-polarization based method will be compared for its model accuracy. Second, the process margin
improvement for polarized and un-polarized illumination will be compared and analyzed for poly layer of sub-60nm
memory device. Finally, method for further enhancing CD error within 5% for polarized OPC model will be discussed.
Over the last couple of years, Design For Manufacturability (DFM) has progressed from concept to practice.
What we thought then is actually applied to the design step to meet the high demand placed upon very high tech devices
we make today. One of the DFM procedures that benefit the lithography process margin is generation of dummy
patterns. Dummy pattern generated at design step enables stable yet high lithography process margin for many of the
high technology device. But actual generation of the dummy pattern is very complex and risky for many of the layer
used for memory devices. Dummy generation for simple pattern layers such as Poly or Isolation layer is not so difficult
since pattern composed for these layers are usually 1 dimensional or very simple 2 dimensional patterns. But for
interconnection layers that compose of complex 2 dimensional patterns, dummy pattern generation is very risky and
requires lots of time and effort to safely place the dummy patterns.
In this study, we propose simple self assembled dummy (SAD) generation algorithm to place dummy pattern
for the complex 2 dimensional interconnection layers. This algorithm automatically self assembles dummy pattern
based on the original design layout, therefore insuring the safety and simplicity of the generated dummy to the original
design. Also we will evaluate SAD on interconnection layer using commercial Model Based Verification (MBV) tool to
verify its applicability for both litho process margin and DFM perspective.
As the k1 factor and minimum feature sizes decrease, the use of optical proximity correction (OPC) is increasing and is getting more complex. The complexity increases the possibility of correction errors like improper placement of edges in the OPC output data such that the printed results will deviate from target design.
In this paper we will describe new modeling method by using 2-dimensional test structures for model based verification of post OPC data. Recently, most of the semiconductor companies implement a system for model based verification (MBV) for post OPC data into a manufacturing data flow.
In case of model based verification, the most important thing is the accuracy of model which is used to detect the potential hot spot and critical errors like pinching-bridging errors and CD variation. For good model accuracy, process change has to be feedback to the model generation step by injecting real wafer information. Therefore, optimization process of 2-dimensional data set is needed.
We proposed new modeling method by using optimization process of calibration data set which consists of 2-dimensional structures. Also, we present results of MBV and discuss about constraints and considerations of model based verification.
The contact hole patterning has been huge challenge in the photolithography since sub-100nm node device. There are many difficulties for NA (Numerical Aperture) and illumination optimization, especially since dense and sparse contact holes are mixed in the same mask. The high NA and OAI (Off Axis Illumination) have strong improvements for pattern fidelity and process margin in case of dense contact holes but DoF (Depth of Focus) margin is a problem for sparse patterns. The lithography engineers have two ways to overcome these contact holes patterning problems. The one is using the resist techniques such as resist thermal flow, SAFIER (Shrink Assist Techniques for Enhanced Resolution), RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) and the other is optimizing illumination and mask layout such as SRAF (Sub Resolution Assist Feature), OAI and PSM (Phase Shift Mask), double exposure. This paper will discuss contact hole patterning results using a combination OAI and SRAF with KrF.
The dawn of the Sub 100nm technology has brought many new exciting challenges for lithography process such as Immersion, OPC, asymmetry illumination, and so on. But, these new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as PR defect, ID bias and Mask Error Factor(MEF) are very important, but the most critical of all for lithography engineer is low process margin created by these technologies.
In this study, we will be presenting the result of the Illumination based assist feature that enhances the lithography process margin for both Exposure Latitude (EL) and Depth Of Focus (DOF), while retaining safety of the scum generation by positioning the assist feature proportional to the illumination for 60nm device. Also, by automatically generating illumination based assist feature on the peripheral region of the mask, we will show that it levels the Critical Dimension (CD) uniformity for pattern of the same dimension located at both cell and peripheral region of the mask. Results will be tested on the mask feature size of 60nm and will be analyzed for both process margin and CD uniformity.
In a world where Sub100nm lithography tool is an everyday household item for device makers, shrinkage of the device is at a rate that no one ever have imagined. With the shrinkage of device at such a high rate, demand placed on Optical Proximity Correction (OPC) is like never before. To meet this demand with respect to shrinkage rate of the device, more aggressive OPC tactic is involved. Aggressive OPC tactics is a must for sub 100nm lithography tech but this tactic eventually results in greater room for OPC error and complexity of the OPC data. Until now, Optical Rule Check (ORC) or Design Rule Check (DRC) was used to verify this complex OPC error. But each of these methods has its pros and cons. ORC verification of OPC data is rather accurate "process" wise but inspection of full chip device requires a lot of money (Computer , software,..) and patience (run time). DRC however has no such disadvantage, but accuracy of the verification is a total downfall "process" wise. In this study, we were able to create a new method for OPC data verification that combines the best of both ORC and DRC verification method. We created a method that inspects the biasing of the OPC data with respect to the illumination condition of the process that's involved. This new method for verification was applied to 80nm tech ISOLATION and GATE layer of the 512M DRAM device and showed accuracy equivalent to ORC inspection with run time that of DRC verification.
Recently, as the design rule shrinks so does the CD tolerance. Therefore, the importance of simulation and OPC accuracy is increasing. In the past, when pattern size was large, rule-based OPC was acceptable but as the design rule shrinks accuracy of OPC turned to model-based OPC and almost all device uses this method. Model-based OPC is based on parameter fitting it has Model-Residual-Error (MRE). Due to this error the accuracy of the model has limitations. Usually variable-threshold or vector model is applied to the model in order to cut down the MRE. But still, size of the MRE is too large compared to CD tolerance. Currently, further development of model-based OPC resulted in creation of both model and rule-based OPC. This is called Hybrid OPC method. Hybrid-OPC method is based on model OPC but MRE can be lowered using rule bias to retarget the design data. But this method makes it difficult to retarget the design data in that rule biasing result is hard to predict after the model-based OPC operation.
In this paper, we propose New Hybrid OPC method that feeds back the MRE calibrated data set to model-based OPC method. By using this method, better OPC model can be made. We will be presenting the result after the method has been applied on sub-60nm device and the capability of this method.
As the minimum feature size of memory devices are getting smaller, model-based OPC accuracy requirements call for highly accurate process modeling and modeling strategies. Therefore, model-based OPC verification process required high accuracy due to unexpected errors on low-k process scheme.
Model of model-based OPC verification (MBV) process has to be accurate in order to detect potential hot spot and human errors, which includes physical design rule violation, mask fabrication rule violation and DB handling errors, and has also suitable speed of fast feedback to OPC and design side in view of DFM.
Recently, model-based OPC tools have progressively advanced in term of modeling. Nevertheless, because we applied extreme off-axis illumination on sub-70nm gate levels, model can not exactly predict the wafer results and have low accuracy.
In this paper, we evaluated several commercial model-based OPC verification (MBV) tools for sub 70nm memory device and compare review results with real wafer results. With the results, we analyze and discuss the major factor for poor OPC and MBV model accuracy for low-k process. Also we will be discussing about suitable speed of feedback to OPC and design part in terms of methods for analysis and categorization of huge number of errors.
We are focus on these two goals for MBV and discuss major factors for consideration. Finally, we would like to suggest optimized procedure for OPC verification by using calibrated models on sub-70nm memory Device.
In recent years, more burden is placed on OPC(Optical Proximity effect Correction) and ORC(Optical Rule Check) like never before due to low process margin caused by adoption of "Low K1" technology on lithography process. Normally, chip is composed of cell, core and periphery regions. Each of these regions has different characteristics patterning wise but usually the region with high density has much more chance for pinch, bridge or killing error and also has small process window. So verification of OPCed data must be highly accurate with fast operation speed. In this paper we developed full chip based ORC(Optical Rule Check)which satisfies both need, accuracy and speed. The result of pinch, bridge and small process window verification of Hybrid ORC will be shown followed by comparison of rule and model ORC methods.
As design rule shrinks down continuously, various technology have been developed to extend the resolution limits of lithography. One of those is Double Exposure Technology(DET). This paper is about not only resolution improvement but also Critical Dimension(CD) variation reduction with DET. As the design rule shrinks below 100nm, the core/peripheral area where we used to think we had sufficient margin is becoming the bottle neck for device fabrication. In this paper, in order to compare optimized single exposure (cell focus) and DET (cell, core/peripheral focus) for critical dimension uniformity(CDU) on cell and core/peripheral area, CDU was measured from wafer by use of simulation and measurement. Gate layer of DRAM device was used for the experiment. Exposure condition for the single exposure was set to crosspole and for DET, dipole and conventional respectively. Optical proximity correction(OPC) was done with in-house simulation tool on stiching area of the double exposure experiment. Same exposure tool and same process condition were used for each experiment and only the exposure condition was changed to compare local CDU, intra-field CDU, wafer CDU to find out how much CD variation can be reduced.
Airborne amine control history for DUV lithography dates back to early 1990's. Environmentally stable resist coupled with air filter system was successfully adopted to cope with the issue. Today's trend toward extending KrF lithography lifetime further, however, demands a hard-to-achieve goal in CD control budget. Small CD change which was acceptable several years ago can no longer be tolerated in current critical technology node. We came to know that CD changes in a different manner for delay time depending on the amine concentration, pattern size, shape, and density. At very low amine concentration, delay time dependency is strongly governed by the chemical composition of the resist material. Relaxation of such dependency could be fulfilled by tuning resist bake condition.
Lens aberration of the exposure tool causes pattern deformation and position shift. As design rule shrinks, the ratio of printed feature size to applied wavelength for optical lithography is driven inexorably toward resolution limit. In this study, we devised an efficient method to evaluate lens aberration using multi-ring pattern on an attenuated phase-shift mask. Adoption of multi-ring pattern can cut down measurement time and improve measurement repeatability. These patterns are uniformly distributed through entire field in 7 by 7 manner. Lens aberration was evaluated by multi-ring pattern array under conventional or off-axis illumination with KrF stepper of NA 0.65. Multi-ring critical dimension (CD) data was discussed together with the issue of lens aberration such as coma, astigmatism, field curvature, etc. We can apply this new measurement technique to select better lens system efficiently. multi-ring, field size, pattern deformation
Wafer-induced-shift caused by bottom anti-reflective coating (BARC) was observed during the misalignment compensation of stepper. This was represented as wafer scale component, that is, shot position dependence across the diameter of the wafer. Measurement error was quantified by comparison between pre- and post-etch pattern alignment data. Typical wafer scale value difference of 0.2ppm in 200mm diameter wafer was observed corresponding to maximum 20nm misalignment in the wafer edge. This is a detrimental value in critical mask step of current device manufacturing, and can be even more serious in next generation design rule adopting 300mm wafer, meaning maximum 30nm false measurement in the wafer edge. To reveal the cause of this phenomenon, the same sequential evaluation was performed without BARC application. No corresponding effect was detected supporting that BARC really caused such wafer-induced-shift. It was found that the wafer-induced-shift amount could be correlated with the size and shape of the alignment monitor pattern. We concluded that the wafer-induced-shift could be minimized by careful adoption of the alignment mark.
KEYWORDS: Scanners, Critical dimension metrology, Photomasks, Etching, Process control, Deep ultraviolet, Semiconducting wafers, Mask making, Optical proximity correction, Control systems
DUV scanner (4x) gate CD control was evaluated and compared with that of DUV stepper (5x) under the concept of total process proximity based correction (TPPC), merging all the process step error correction from mask fabrication to wafer etch process. We found that different iso-dense bias should be applied in the case of scanner. This is mainly caused by different optical proximity effect (DI-mask CD), that is, scanner shows nearly constant optical proximity effect regardless of the size of pattern CD while that of stepper is strongly dependent upon the size of pattern CD. Application of the concept of TPPC in DUV scanner enabled us to control FI CD within specification. A correction rule table was experimentally obtained using TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.
In this study, we investigated mask errors, photo errors with attenuated phase shift mask and off-axis illumination, and etch errors in dry etch condition. We propose that total process proximity correction (TPPC), a concept merging every step error correction, is essential in lithography process when minimum critical dimension (CD) smaller than the wavelength of radiation. A correction rule table was experimentally obtained applying TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.
A new methodology using the admittance diagram is proposed for optimization of an antireflective layer (ARL) and the simple ARL optimizer with its own 2D and 3D dynamic graphic tools is developed. Under the methodology, the overall dependency of the reflectivity on optical properties of ARLs can be viewed from a single 2D graph, and the tolerance of process step for the optimally designed ARL can be evaluated geometrically. And also, the optimal condition of an ARL for DUV lithography process is determined by our optimizer and its performance is simulated from our own lithography simulator based on rigorous vector theory. Finally, the effect of ARLs are investigated experimentally, and their results are compared with simulation results.
The depth of focus in sub-half micron lithography is about plus or minus 5 micrometers , several factors, such as field image curvature, circuit topography, wafer flatness error and auto-focus errors, reduce the usable focus margin. To minimize these focus margin decreasing factors, multi-point focus detection and/or field chip leveling control should be required before every exposure. Even the cases, global deviations of wafer and chuck flatness errors are being corrected with the good field leveling system, the focus sensing accuracy must stay in the plus or minus 0.075 micrometers region for all the exposure field. In the conventional optical auto- focus systems, small spot sizes probe beam was used, and the focus signal can be affected strongly by local variations in reflectance, scattering on the wafer surface and wafer flatness. Whereas probe beam scan type auto-focus system, newly developed in this work, has a large focus measurement area, and it averages out the errors which decrease the usable depth of focus. In this work, a new optical auto-focus system for sub-half micron lithography tools will be presented and its characteristics and applications will be discussed. It is composed of a probe beam scan mirror and a position sensing detector, and is insensitive to the structures on the wafer surface. Also, the theoretical analysis of focus measurement error, per the probe beam width and wafer pattern topology will be discussed.
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