Dr. Chidam G. Kallingal Profile

Dr. Chidam G. Kallingal

Manager, TD Global Engineering Support at GLOBALFOUNDRIES Inc

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Publications (10)

Proceedings Article | 20 March 2018 Presentation + Paper

Efficient full-chip SRAF placement using machine learning for best accuracy and improved consistency

Shibing Wang, Stanislas Baron, Nishrin Kachwala, Chidam Kallingal, Dezheng Sun, Vincent Shu, Weichun Fong, Zero Li, Ahmad Elsaid, Jin-Wei Gao, Jing Su, Jung-Hoon Ser, Quan Zhang, Been-Der Chen, Rafael Howell, Stephen Hsu, Larry Luo, Yi Zou, Gary Zhang, Yen-Wen Lu, Yu Cao

Proceedings Volume 10587, 105870N (2018) https://doi.org/10.1117/12.2299421

KEYWORDS: SRAF, Machine learning, Optical proximity correction, Photomasks, Lithography, Model-based design, Source mask optimization, Computational lithography, Image processing

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Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.

Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).

Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.

ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.

In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.

Proceedings Article | 24 March 2017 Presentation + Paper

Using heuristic optimization to set SRAF rules

ChangAn Wang, Norman Chen, Chidam Kallingal, William Wilkinson, Jian Liu, Alan Leslie

Proceedings Volume 10147, 1014706 (2017) https://doi.org/10.1117/12.2258233

KEYWORDS: SRAF, Printing, Semiconducting wafers, Matrices, Silicon, Lithography, Manufacturing, Image processing, Optical proximity correction, Genetic algorithms, Optimization (mathematics), Logic, Algorithm development, Photomasks

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Proceedings Article | 18 March 2015 Paper

Quantitative evaluation of manufacturability and performance for ILT produced mask shapes using a single-objective function

Heon Choi, Wei-long Wang, Chidam Kallingal

Proceedings Volume 9427, 94270I (2015) https://doi.org/10.1117/12.2087111

KEYWORDS: Photomasks, Resolution enhancement technologies, Manufacturing, SRAF, Neodymium, Optical proximity correction, Photovoltaics, Optical lithography, Lithography, Semiconducting wafers

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The continuous scaling of semiconductor devices is quickly outpacing the resolution improvements of lithographic exposure tools and processes. This one-sided progression has pushed optical lithography to its limits, resulting in the use of well-known techniques such as Sub-Resolution Assist Features (SRAF’s), Source-Mask Optimization (SMO), and double-patterning, to name a few. These techniques, belonging to a larger category of Resolution Enhancement Techniques (RET), have extended the resolution capabilities of optical lithography at the cost of increasing mask complexity, and therefore cost. One such technique, called Inverse Lithography Technique (ILT), has attracted much attention for its ability to produce the best possible theoretical mask design. ILT treats the mask design process as an inverse problem, where the known transformation from mask to wafer is carried out backwards using a rigorous mathematical approach. One practical problem in the application of ILT is the resulting contour-like mask shapes that must be “Manhattanized” (composed of straight edges and 90-deg corners) in order to produce a manufacturable mask. This conversion process inherently degrades the mask quality as it is a departure from the “optimal mask” represented by the continuously curved shapes produced by ILT. However, simpler masks composed of longer straight edges reduce the mask cost as it lowers the shot count and saves mask writing time during mask fabrication, resulting in a conflict between manufacturability and performance for ILT produced masks1,2. In this study, various commonly used metrics will be combined into an objective function to produce a single number to quantitatively measure a particular ILT solution’s ability to balance mask manufacturability and RET performance. Several metrics that relate to mask manufacturing costs (i.e. mask vertex count, ILT computation runtime) are appropriately weighted against metrics that represent RET capability (i.e. process-variation band, edge-placement-error) in order to reflect the desired practical balance. This well-defined scoring system allows direct comparison of several masks with varying degrees of complexities. Using this method, ILT masks produced with increasing mask constraints will be compared, and it will be demonstrated that using the smallest minimum width for mask shapes does not always produce the optimal solution.

Proceedings Article | 12 April 2013 Paper

Benchmarking study of 3D mask modeling for 2X and 1X nodes

ChangAn Wang, Chao-Chun Liang, Huikan Liu, Chidam Kallingal, Derren Dunn, James Oberschmidt, Jaione Tirapu Azpiroz

Proceedings Volume 8683, 86831A (2013) https://doi.org/10.1117/12.2011485

KEYWORDS: Photomasks, 3D modeling, Optical proximity correction, Performance modeling, Data modeling, Calibration, Critical dimension metrology, Metals, Error analysis, Diffraction

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Proceedings Article | 16 March 2009 Paper

C-quad polarized illumination for back end thin wire: moving beyond annular illumination regime

Sohan Mehta, Hyung-Rae Lee, Bassem Hamieh, Chidam Kallingal, Itty Matthew, Ramya Viswanathan, Derren Dunn

Proceedings Volume 7274, 72742Y (2009) https://doi.org/10.1117/12.814296

KEYWORDS: Polarization, Line edge roughness, Optical lithography, Semiconducting wafers, Diffraction, Fiber optic illuminators, Fourier transforms, Critical dimension metrology, Lithography, Reticles

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Proceedings Article | 17 October 2008 Paper

Improvements in accuracy of dense OPC models

Chidam Kallingal, James Oberschmidt, Ramya Viswanathan, Amr Abdo, OSeo Park

Proceedings Volume 7122, 71221Q (2008) https://doi.org/10.1117/12.801695

KEYWORDS: Optical proximity correction, Diffusion, Data modeling, Optimization (mathematics), Calibration, Critical dimension metrology, Cadmium, Semiconducting wafers, Model-based design, Photoresist processing

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Proceedings Article | 2 April 2008 Paper

The comparison of OPC performance and run time for dense versus sparse solutions

Amr Abdo, Ian Stobert, Ramya Viswanathan, Ryan Burns, Klaus Herold, Chidam Kallingal, Jason Meiring, James Oberschmidt, Scott Mansfield

Proceedings Volume 6924, 69243G (2008) https://doi.org/10.1117/12.772902

KEYWORDS: Optical proximity correction, Data modeling, Scanning electron microscopy, Computer simulations, Calibration, Performance modeling, Resolution enhancement technologies, Semiconducting wafers, Lithography, Wafer-level optics

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Proceedings Article | 20 October 2006 Paper

Correlation between OPC model accuracy and image parameters

Chidam Kallingal, Norman Chen

Proceedings Volume 6349, 63494M (2006) https://doi.org/10.1117/12.686240

KEYWORDS: Data modeling, Calibration, Optical proximity correction, Critical dimension metrology, Diffusion, Semiconducting wafers, Image quality, Photomasks, Process modeling, Image analysis

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Proceedings Article | 4 May 2005 Paper

Topography impacts on line-width control for gate level lithography

Allen Gabor, Scott Halle, Chidam Kallingal

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.600697

KEYWORDS: Semiconducting wafers, Reflectivity, Neodymium, Silicon, Lithography, Control systems, Critical dimension metrology, Oxides, Photoresist processing, Chemical mechanical planarization

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Proceedings Article | 2 June 2003 Paper

Faster qualification of 193-nm resists for 100-nm development using photo cell monitoring

Chris Jones, Chidam Kallingal, Mary Zawadzki, Nazneen Jeewakhan, Nazila Kaviani, Prakash Krishnan, Arthur Klaum, Joel Van Ess

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.504591

KEYWORDS: Photoresist materials, Semiconducting wafers, Optical lithography, Inspection, Etching, Critical dimension metrology, Scanning electron microscopy, Wafer testing, Semiconductors, Photoresist processing

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The development of 100-nm design rule technologies is currently taking place in many R&D facilities across the world. For some critical alyers, the transition to 193-nm resist technology has been required to meet this leading edge design rule. As with previous technology node transitions, the materials and processes available are undergoing changes and improvements as vendors encounter and solve problems. The initial implementation of the 193-nm resits process did not meet the photolithography requirements of some IC manufacturers due to very high Post Exposure Bake temperature sensitivity and consequently high wafer to wafer CD variation. The photoresist vendors have been working to improve the performance of the 193-nm resists to meet their customer's requirements. Characterization of these new resists needs to be carried out prior to implementation in the R&D line. Initial results on the second-generation resists evaluated at Cypress Semicondcutor showed better CD control compared to the aelrier resist with comparable Depth of Focus (DOF), Exposure Latitute, Etch Resistance, etc. In addition to the standard lithography parameters, resist characterization needs to include defect density studies. It was found that the new resists process with the best CD control, resulted in the introduction of orders of magnitude higher yield limiting defects at Gate, Contact adn Local Interconnect. The defect data were shared with the resists vendor and within days of the discovery the resist vendor was able to pinpoint the source of the problem. The fix was confirmed and the new resists were successfully released to production. By including defect monitoring into the resist qualification process, Cypress Semiconductor was able to 1) drive correction actions earlier resulting in faster ramp and 2) eliminate potential yield loss. We will discuss in this paper how to apply the Micro Photo Cell Monitoring methodology for defect monitoring in the photolithogprhay module and the qualification of 193nm resist processes.

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