We demonstrate a vertical-junction, carrier-injection, micro-ring modulator that is fabricated using AIM Photonics’ 300 mm Quantum FLEX Platform which shows results with high modulation efficiency and a large ON-OFF ratio. The modulator device includes a ring and a single-bus, straight waveguide. The ring has a radius of 7 μm and a 220 nm silicon-on-insulator (SOI) waveguide is used both for the ring and the straight waveguides with a rib structure of 110-nm slab thickness. The width of the core waveguide is 550 nm for both the ring and the straight waveguides. The slab width between the full-height silicon core and contact area is kept at 1 μm on both sides from the 550-nm core. The coupling gap between the ring and the bus waveguide is designed to be 150 nm. To make the waveguide core vertical junction, the upper half of the core is n-doped and the lower half is p-doped. To have a smooth electrical connectivity between the core and the contact area, three-level doping is applied where the core is doped with the minimum concentration and the contact silicon area is doped with the highest concentration. The modulator is tested with a tunable laser over a 100-nm window extending from 1485 nm to 1585 nm. The light is coupled to the modulator using grating couplers which are used to couple input and output light. The vertical junction shows excellent direct current (DC) I-V characteristics and the modulator performs at high modulation efficiency of about 1.14 nm and a large ON-OFF ratio of about 21 dB at 1.0 V.
In this work we explain the methodology and techniques for building an end-to-end design enablement (DE) platform from component design to process design kit (PDK) release for silicon photonics-based photonic integrated circuit (PIC) design. Elements of the DE include: component design, layout and test site development, measurement infrastructure and PDK development. Our methodology builds on the best practices followed in CMOS and RF foundries but adds unique features specific to silicon photonics. The DE flow is developed on the American Institute for Manufacturing Integrated Photonics’ (AIM Photonics) 300 mm silicon photonic technologies manufactured in a limited-volume foundry at the Albany Nanotech Complex, in Albany, NY. For component development, the AIM Photonics PDK offers a process stack file supported in Lumerical platform that applies linewidth corrections and doping information to imported layouts increasing the efficiency and accuracy of the design. For test sites, an automated layout and connectivity framework is explained that allows users to generate a layout from spreadsheet inputs that is also compatible with automated waferscale measurements. AIM Photonics PDKs include layout, models and design-rule-check (DRC) tools that are offered across multiple platforms. The DRC decks are offered in commercial tools such as Cadence and Synopsys, as well as KLayout. We present features of layouts and communication with schematics. In addition, we also explain techniques for processing and analyzing measured statistical data and extracting platform specific compact models. Presenting this methodology to the wider community is integral to the mission of AIM Photonics and will be of immense benefit particularly to small organizations engaged in prototype development.
The reduction of optical loss for integrated photonics I/O is an important area of active research. Edge coupling (end-firing) is a key I/O technology, having advantages over grating couplers in terms of spectral bandwidth and lower insertion loss1. Low-loss edge coupling into silicon waveguides will be critical to datacenters and telecommunications systems in order to help accommodate the aggressive growth of data analytics applications2. In this work, we investigate the coupling losses from optical fiber (SMF-28) into on-chip silicon waveguides using silicon nitride edge couplers with varying chip facet angles. The expected losses were simulated using Three Dimensional Finite-Difference Time-Domain (3D-FDTD) modelling and measured experimentally to close the design-fabrication loop. The chips were produced within a state-of-the-art 300 mm CMOS foundry, using edge couplers from the foundry Process Design Kit (PDK). During optimization of the photolithography and dry etching process, the facet angle deviation from 90° was minimized. Insertion loss of the SiN edge coupler was investigated via transmission measurements utilizing both cleaved fibers and fiber V-grooves. Facet angles varied from approximately 75°–90° were tested for insertion loss and trends were consistent with the 3D-FDTD modelling. Measurements were performed over a range of 1450–1650 nm using a tunable laser source and optical power meter. In addition, facet insertion loss was isolated by using propagation loss data from an in-line testing tool that measured silicon waveguides propagation losses, on wafer and in the same wavelength band.
The American Institute for Manufacturing Integrated Photonics (AIM Photonics) runs a silicon photonics multi-project wafer (MPW) program providing riders with access to silicon photonic devices and circuits fabricated in a state-of-the-art 300 mm CMOS line. Current MPW offerings include both silicon and silicon nitride waveguides, GHz modulation/detection, electro-optic switches and filters, low-loss edge coupling, three metal levels, and supports operation in the O, C, and L bands. Often propagation loss is not prioritized for active MPW runs in favor of other key parameters such as modulation speeds, photodiode responsivity, device size, spectral bandwidths, etc. However, for areas such as quantum technology, sensors, LiDAR, and data communications it is an imperative to incorporate both low-loss waveguides and active devices on a single die. These application areas require lower propagation losses because they either use single photons, high Q resonators, and/or require high efficiency coupling for lasers/SOAs. As part of our updated MPW integration, we have demonstrated losses of 1.1 dB/cm in Si strip waveguides and 0.4 dB/cm in SiN strip waveguides, a reduction of 1.4 dB/cm and 1.6 dB/cm, respectively, from our published MPW values.
A novel process design kit (PDK) offering providing seamless access to the Albany NanoTech Complex’s 300mm foundry with a mission to promote silicon photonics technology is demonstrated. Unlike traditional pure-play foundries, we have developed a framework that allows our PDKs to contain libraries developed by internal and external domain experts. In addition to integrated Electronic Photonic Design Automation (EPDA) platforms, our PDK is also released in an alternate PIC design flow that the lowers the cost barrier for organizations. Further, our PDKs target a broad application space that includes telecom as well emerging areas such as sensors and quantum photonics – all with the ability for onboard light sources. A PDK from American Institute of Manufacturing (AIM Photonics) will be discussed that demonstrates these features.
Recent integrated optical phased array architectures, results, and applications will be reviewed. Beam-steering optical phased arrays monolithically integrated with on-chip rare-earth-doped lasers and heterogeneously integrated with CMOS driving electronics will be shown. Passive integrated optical phased arrays that focus radiated light to tightly-confined spots in the near field and that generate quasi-Bessel beams will be discussed. Finally, integrated-phased-array-based visible-light holographic displays will be proposed as a scalable solution towards the next generation of augmented-reality head-mounted displays; passive near-eye holographic displays, visible-light liquid-crystal modulators, and liquid-crystal-based visible-light phased arrays will be presented.
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