The demands imposed by shrinking design rules for sub 20 nm technology on lithographic resolution are driving
many avenues of research and development in an attempt to provide a robust and affordable solution for high
volume manufacturing. Currently, pitch splitting techniques, such as self-aligned double and quadruple patterning
(SADP or SAQP) and litho-etch litho-etch …(LELE…), are being used to bridge the gap to next
generation ;lithographic techniques. Cost of ownership (CoO), process window improvements and defectivity are
opportunities and concerns for extensions of these approaches, such as resist sliming on sidewall-image transfer
(SIT) processes like SADP or SAQP. A spin-on resist slimming approach is implemented with line and space resist
to explore process window improvements. The effects of typical process conditions and incoming variability are
studied using a custom design of experiments. The optimized process is then used to evaluate process window gain
compared to the process of record.
The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.
Reduced resist consumption (RRC) process is used to reduce chemical shot sizes by 75% or more. However, as we move to smaller technology nodes, the impurities in RRC solvents are becoming increasingly more problematic. In this study, a series of experiments were conducted to reduce total defectivity via RRC process optimization. The 20nm metal layer is optimized for defect reduction at the OPL/BARC interface. This study looks at the effects of no RRC, static RRC dispense condition, dynamic RRC dispense condition, the number of RRC puddles, puddle times and post apply bake (PAB) temperatures. Overall, a 45% reduction in total raw defects is achieved over current production recipes. The reduction, however, comes at the cost of an increase in line and space defects and single line open (SLO) defects. The line and space defects increased by 62% and the SLO defects had a 40% increase.
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