Process window qualification using focus-exposure wafers is an essential step in lithography and a key use case for CD-SEM metrology. An automated analysis using the correlation between CD and focus/dose is easily possible but rarely done due to missing safety checks. Pattern fidelity that is analyzed by eye and problematic focus/dose conditions that may cause pattern degradation are excluded by hand. Specifically, when EUV lithography is utilized for exposing the most critical layers, roughness estimation becomes much more important, as it will restrict the process window further. We develop and describe unbiased and stable roughness estimates for contact hole patterns and integrate them into the process window analysis pipeline and inline monitoring routine. The analysis goes beyond simple roughness values and can detect a variety of possible CD-SEM measurement problems and shape deviations as well. Furthermore, we introduce a novel image-based machine-learning approach to detect outliers and quantify defective or abnormal patterns. Notably, the underlying model does not require knowledge of the types of CD features or design information for which outliers should be detected. We demonstrate that the approach can reliably detect local defects and a variety of other pattern anomalies. Using the generated visualizations, images with anomalous features can be flagged automatically and the locations of the defects or deviations are pinpointed. The approach yields not only the final missing piece in automated process window qualification, but also new opportunities to monitor pattern fidelity in lithographical semi-conductor processes.
In most leading-edge technologies, first layers usually are more critical than later layers. For some technologies, however, most critical layers are in mid-of line. On such technologies, less advanced equipment is used for first layers. Because such tools are not so stable, the overlay variation must be compensated on advanced tools used for later layers. Wafer-to-wafer variation is typically corrected by wafer alignment. By standard wafer alignment, intra-field variations are usually not corrected. Because of the instability of the older tools, additional marks to compensate intra-field variation were measured on advanced tools. This reduces the wafer-to-wafer variation but causes throughput loss. Therefore, sampling plans were optimized to reduce the number of intra-field marks by 50%. This was verified by run-to-run simulations and experiments.
Non-linear overlay deformation is a well-known problem in critical lithography steps. A significant root cause is nonuniform stress, often caused by high temperature processes. Non-uniform stress in the wafer causes vertical deformation of the wafer, which can be measured by topography measurement equipment. In this case study, clustering is done on the topography data to sort each wafer into groups. Using the context information from the clustering, overlay feedback is computed on a wafer level basis. The evaluation of the approach is done with a run-to-run simulation, which allows optimization of this method and evaluation of the on-product overlay performance improvement. In the analysis, different wafer zones are distinguished to characterize the improvement potential for the different zones.
Wafer leveling data are usually used inside the exposure tool for ensuring good focus, then discarded. This paper describes the implementation of a monitoring and analysis solution to download these data automatically, together with the correction profiles applied by the scanner. The resulting height maps and focus residuals form the basis for monitoring metrics tailored to catching tool and process drifts and excursions in a high-volume manufacturing (HVM) environment.
In this paper, we present four six cases to highlight the potential of the method: wafer edge monitoring, chuck drift monitoring, correlations between focus residuals and overlay errors, and pre-process monitoring by chuck fingerprint removal.
High order overlay and alignment models require good coverage of overlay or alignment marks on the wafer. But dense sampling plans are not possible for throughput reasons. Therefore, sampling plan optimization has become a key issue. We analyze the different methods for sampling optimization and discuss the different knobs to fine-tune the methods to constraints of high volume manufacturing. We propose a method to judge sampling plan quality with respect to overlay performance, run-to-run stability and dispositioning criteria using a number of use cases from the most advanced lithography processes.
This paper focuses on orthogonal model corrections where model parameters do not influence each other as long as the
measurement layout is sufficiently symmetric. For the grid correction we used Zernike polynomials, and for the intrafield
correction we used a two-dimensional set of Legendre polynomials. We enabled these corrections by developing a
transformation matrix as an exposure tool is incapable of correcting such orthogonal polynomials. Simulation with
OVALiS shows that the linear parameters get stabilized by several factors when using a combined Zernike/Legendre
model. The correlation between linear and higher order parameters disappears, and overlay mean plus 3-sigma improves
up to ~15–20%. Simulated data agrees well with experimental and electrical data. Additionally, we introduced an
interpolated metric that probed the wafer and field with a dense grid. This interpolated metric showed that the
Zernike/Legendre model-based correction does not cause over-correction like that seen on standard polynomial models.
We have tested higher order process corrections comprehensively by enabling an orthogonal model, as well as by
making use of interpolated metrics to monitor the overlay performance. These orthogonal models can be implemented in
the production line based on inline overlay data where interpolated metrics will ensure that there is no over-correction
and no negative impact on product.
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