Mr. Eric Milligan Profile

Eric Milligan

at Bruker Nano Inc

SPIE Involvement:

Author

Publications (1)

Proceedings Article | 18 March 2016 Paper

Device level 3D characterization using PeakForce AFM

Padraig Timoney, Xiaoxiao Zhang, Alok Vaid, Sean Hand, Jason Osborne, Eric Milligan, Adam Feinstein

Proceedings Volume 9778, 97781A (2016) https://doi.org/10.1117/12.2220152

KEYWORDS: Atomic force microscopy, Semiconducting wafers, 3D metrology, Transmission electron microscopy, Metrology, Pulmonary function tests, Metals, Scatterometry, Diffractive optical elements, Overlay metrology

Read Abstract +

Traditional metrology solutions face a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. With advent of advanced technology nodes and 3D processing, an increasing need is emerging for in-die metrology including across-structure and structure-to-structure characterization. A myriad of work has emerged in the past few years intending to address these challenges from various aspects; in-die OCD with reduced spot size and tilt beam on traditional critical dimension scanning electron microscopy (CDSEM) for height measurements. This paper explores the latest capability offered by PeakForce^TM Tapping Atomic Force Microscopy (PFT-AFM). The use of traditional harmonic tapping mode for scanning high aspect ratio, and complex “3D” wafer structures, results in limited depth probing capability as well as excessive tip wear. These limitations arise due to the large tip-sample interaction volume in such confined spaces. PeakForce Tapping eliminates these limitations through direct real time control of the tip-sample interaction contact force. The ability of PeakForce to measure, and respond directly to tip- sample interaction forces results in more detailed feature resolution, reduced tip wear, and improved depth capability. In this work, the PFT-AFM tool was applied for multiple applications, including the 14nm fin and replacement metal gate (RMG) applications outlined below. Results from DOE wafers, detailed measurement precision studies and correlation to reference metrology are presented for validation of this methodology. With the fin application, precision of 0.3nm is demonstrated by measuring 5 dies with 10 consecutive runs. Capability to resolve within-die and localized within-macro height variation is also demonstrated. Results obtained from the fin measurements support the increasing trend that measurements in the scribe line may not accurately represent in-die geometry, thus indicating the increasing need to measure the real device area. In-die measurement capability of peak force tapping AFM on wafers at post-poly-removal step in the RMG module is also evaluated. Precision of 1.22nm for the fin height under the gate, 1.06nm for the total gate height, and 0.77nm for the overburden are achieved in this application on a semidense structure. To the knowledge of the authors, this is the first demonstration of a robust in-die measurement of the fin height under the gate.

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years