KEYWORDS: Design for manufacturing, Databases, Rule based systems, Semiconducting wafers, System identification, Visualization, Photomasks, Lutetium, Microelectronics, Design for manufacturability
In this paper we combined the hotspot pattern library and the rule-based scoring system into a modularized hotspot-checking rule deck running on an automatic flow. Several DFM (design for manufacture) properties criteria will be defined to build a “score board” for hotspot candidates. When hotspots in the input design are highlighted, the scoring system can identify whether a hotspot is a high risk hotspot or not, and define the severity of the hotspots by extracted DFM properties. The automatic flow will detect which layers are contained in the design then generate a modular rule deck with several corresponding hotspot check modules. The flow also takes snapshots of the high risk hotspots according to the score board automatically. After all the essential hotspot data is collected, the flow will automatically create an HTML-format report which has histograms of properties and overview graph that shows the distribution of hotspots. The aforementioned HTML report containing scored DFM properties and snapshots can help result-viewers to identify the high risk hotspots on the design quickly; namely, users can examine hotspots by snapshots without loading the whole design into layout viewer tools. By comparing the hotspot checking result with real defects from wafer data, a true hotspot’s values of DFM properties can be obtained. We believe this is helpful for users to improve their hotspot rules in accuracy.
The Mask Data Correctness Check (MDCC) is a reticle-level, multi-layer DRC-like check evolved from mask rule
check (MRC). The MDCC uses extended job deck (EJB) to achieve mask composition and to perform a detailed check
for positioning and integrity of each component of the reticle. Different design patterns on the mask will be mapped to
different layers. Therefore, users may be able to review the whole reticle and check the interactions between different
designs before the final mask pattern file is available. However, many types of MDCC check results, such as errors from
overlapping patterns usually have very large and complex-shaped highlighted areas covering the boundary of the design.
Users have to load the result OASIS file and overlap it to the original database that was assembled in MDCC process on
a layout viewer, then search for the details of the check results. We introduce a quick result-reviewing method based on
an html format report generated by Calibre® RVE. In the report generation process, we analyze and extract the essential
part of result OASIS file to a result database (RDB) file by standard verification rule format (SVRF) commands.
Calibre® RVE automatically loads the assembled reticle pattern and generates screen shots of these check results. All the
processes are automatically triggered just after the MDCC process finishes. Users just have to open the html report to
get the information they need: for example, check summary, captured images of results and their coordinates.
The mask composition checking flow is an evolution of the traditional mask rule check (MRC). In order to differentiate
the flow from MRC, we call it Mask Data Correctness Check (MDCC). The mask house does MRC only to identify
process limitations including writing, etching, metrology, etc. There still exist many potential errors that could occur
when the frame, main circuit and dummies all together form a whole reticle. The MDCC flow combines the design rule
check (DRC) and MRC concepts to adapt to the complex patterns in today’s wafer production technologies. Although
photomask data has unique characteristics, the MRC tool in Calibre® MDP can easily achieve mask composition by using
the Extended MEBES job deck (EJB) format. In EJB format, we can customize the combination of any input layers
in an IC design layout format, such as OASIS. Calibre MDP provides section-based processing for many standard verification
rule format (SVRF) commands that support DRC-like checks on mask data. Integrating DRC-like checking with
EJB for layer composition, we actually perform reticle-level DRC, which is the essence of MDCC. The flow also provides
an early review environment before the photomask pattern files are available. Furthermore, to incorporate the
MDCC in our production flow, runtime is one of the most important indexes we consider. When the MDCC is included
in the tape-out flow, the runtime impact is very limited. Calibre, with its multi-threaded processes and good scalability, is
the key to achieving acceptable runtime. In this paper, we present real case runtime data for 28nm and 14nm technology
nodes, and prove the practicability of placing MDCC into mass production.
Photolithography process is getting more and more sophisticated for wafer production following Moore’s law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers’ judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.
For many maskshops, designed parallel mask data preparation (MDP) flows accompanying with a final data comparison
are viewed as a reliable method that could reduce quality risks caused by mis-operation. However, in recent years, more
and more mask data mistakes have shown that present parallel MDP flows could not capture all mask data errors yet. In
this paper, we will show major failure models of parallel MDP flows from analyzing MDP quality accidents and share
our approaches to achieve further improvement with mask suppliers together.
For those wafer fabs that have no their own maskshops, the main target of mask quality department is to gain stable mask
quality performance through effective supplier management, and therefore achieves competitive business results. After
dealing with lots of mask data preparation (MDP) quality problems with suppliers, we have found that incomplete
change management procedures are one of major sources that induce incorrect mask data for writing. This article will
share our experience in how to enhance change management flows with mask suppliers together and will also show the
utility after a series of flow improvement actions.
In semiconductor industry, many wafer fabs acquire masks from qualified suppliers because they do not have in-house
maskshops. Under the circumstances, for these fabs, their main objectives of mask supplier management are to carry out
gaining stable quality performance with punctual delivery and acceptable prices. At present, interests in mask supplier
management are launching into mask data preparation (MDP) field when it's beginning to face raised challenges to
output correct results all the time. These incoming tasks are mainly due to increasingly complicated MDP demand from
wafer fabs for implementing various approaches on masks and tape-out to support wafer production and tight cycle-time
control. In this paper, it shows major factors of MDP quality issues from analyzing past accidents in our suppliers and
proposes possible approaches for achieving further improvement.
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