Dr. Evert C. Mos Profile

Dr. Evert C. Mos

at ASML Netherlands BV

SPIE Involvement:

Author

Publications (10)

Proceedings Article | 20 March 2019 Paper

Holistic feedforward control for the 5 nm logic node and beyond

Henry Megens, Ralph Brinkhof, Igor Aarts, Haico Kok, Leendertjan Karssemeijer, Gijs ten Haaf, Shawn Lee, Daan Slotboom, Chris de Ruiter, Irina Lyulina, Simon Huisman, Stefan Keij, Evert Mos, Wim Tel, Manouk Rijpstra, Emil Schmitt-Weaver, Kaustuve Bhattacharyya, Robert Socha, Boris Menchtchikov, Michael Kubis, Jan Mulkens

Proceedings Volume 10961, 109610K (2019) https://doi.org/10.1117/12.2515449

KEYWORDS: Lithographic process control, Semiconducting wafers, Optical alignment, Overlay metrology, Sensors, Distortion, Scanners, Logic, Metrology, Process control

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Proceedings Article | 25 March 2016 Paper

Holistic overlay control for multi-patterning process layers at the 10nm and 7nm nodes

Leon Verstappen, Evert Mos, Peter Wardenier, Henry Megens, Emil Schmitt-Weaver, Kaustuve Bhattacharyya, Omer Adam, Grzegorz Grzela, Joost van Heijst, Lotte Willems, Jochem Wildenberg, Velislava Ignatova, Albert Chen, Frank Elich, Bijoy Rajasekharan, Lydia Vergaij-Huizer, Brian Lewis, Marc Kea, Jan Mulkens

Proceedings Volume 9778, 97781Y (2016) https://doi.org/10.1117/12.2230390

KEYWORDS: Process control, Overlay metrology, Process modeling, Semiconducting wafers, Metrology, Scanners, Target detection, Lithium, Optical alignment, Time metrology

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Multi-patterning lithography at the 10-nm and 7-nm nodes is driving the allowed overlay error down to extreme low values. Advanced high order overlay correction schemes are needed to control the process variability. Additionally the increase of the number of split layers results in an exponential increase of metrology complexity of the total overlay and alignment tree. At the same time, the process stack includes more hard-mask steps and becomes more and more complex, with as consequence that the setup and verification of the overlay metrology recipe becomes more critical. All of the above require a holistic approach that addresses total overlay optimization from process design to process setup and control in volume manufacturing. In this paper we will present the holistic overlay control flow designed for 10-nm and 7-nm nodes and illustrate the achievable ultimate overlay performance for a logic and DRAM use case. As figure 1 illustrates we will explain the details of the steps in the holistic flow. Overlay accuracy is the driver for target design and metrology tool optimization like wavelength and polarization. We will show that it is essential to include processing effects like etching and CMP which can result in a physical asymmetry of the bottom grating of diffraction based overlay targets. We will introduce a new method to create a reference overlay map, based on metrology data using multiple wavelengths and polarization settings. A similar approach is developed for the wafer alignment step. The overlay fingerprint correction using linear or high order correction per exposure (CPE) has a large amount of parameters. It is critical to balance the metrology noise with the ultimate correction model and the related metrology sampling scheme. Similar approach is needed for the wafer align step. Both for overlay control as well as alignment we have developed methods which include efficient use of metrology time, available for an in the litho-cluster integrated metrology use. These methods include a novel set models that efficiently describe different process fingerprints. We will explain the methods and show the benefits for logic and DRAM use cases.

SPIE Journal Paper | 1 October 2011

Toward 22 nm: fast and effective intrafield monitoring and optimization of process windows and critical dimension uniformity

Christopher Bencher, Jo Finders, Ilan Englard, Yaron Cohen, Amir Sagiv, Michael Ben-Yishai, Shmoolik Mangan, Huixiong Dai, Chris Ngai, Kfir Dotan, Roel Knops, Orion Mouraille, Evert Mos, Alexander Kremer

JM3, Vol. 10, Issue 04, 043003, (October 2011) https://doi.org/10.1117/12.10.1117/1.3641409

KEYWORDS: Photomasks, Semiconducting wafers, Critical dimension metrology, Lithography, Metrology, Inspection, Scanners, Optimization (mathematics), Double patterning technology, Wavefronts

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Proceedings Article | 20 April 2011 Paper

Towards 22 nm: fast and effective intra-field monitoring and optimization of process windows and CDU

Yaron Cohen, Jo Finders, Roel Knops, Orion Mouraille, Ingrid Minnaert-Janssen, Frank Duray, Evert Mos, Alexander Kremer, Amir Sagiv, Shmoolik Mangan, Michael Ben Yishay, Huixiong Dai, Christopher Bencher, Christopher Ngai, Kfir Dotan, Ilan Englard

Proceedings Volume 7971, 79711N (2011) https://doi.org/10.1117/12.881657

KEYWORDS: Photomasks, Semiconducting wafers, Metrology, Lithography, Critical dimension metrology, Scanners, Inspection, Double patterning technology, Optimization (mathematics), Wavefronts

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Proceedings Article | 29 March 2011 Paper

Litho process control via optimum metrology sampling while providing cycle time reduction and faster metrology-to-litho turn around time

K.-H. Chen, Jacky Huang, W.-T. Yang, C.-M. Ke, Y.-C. Ku, John Lin, Kaustuve Bhattacharyya, Evert Mos, Mir Shahrjerdy, Maurits van der Schaar, Steffen Meyer, Spencer Lin, Jon Wu, Sophie Peng, Albert Li, Nikki Chang, Roy Chu, Cathy Wang

Proceedings Volume 7971, 797105 (2011) https://doi.org/10.1117/12.879218

KEYWORDS: Semiconducting wafers, Metrology, Overlay metrology, Time metrology, Process control, Lithography, Tin, Feedback control, Scanners, Optical lithography

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Proceedings Article | 17 March 2009 Paper

Dense lines created by spacer DPT scheme: process control by local dose adjustment using advanced scanner control

Jo Finders, Mircea Dusa, Bert Vleeming, Timon Fliervoet, Birgitt Hepp, Henry Megens, Remco Groenendijk, John Quaedackers, Evert Mos, Christian Leewis, Frank Bornebroek, Mireille Maenhoudt, Marc Leblans, Tom Vandeweyer, Gayle Murdoch, Efrain Altamirano Sanchez

Proceedings Volume 7274, 72740R (2009) https://doi.org/10.1117/12.814091

KEYWORDS: Semiconducting wafers, Etching, Critical dimension metrology, Metrology, Scatterometry, Scanning electron microscopy, Scanners, Process control, Lithography, Optical lithography

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Proceedings Article | 24 May 2004 Paper

Overlay advanced process control for foundry application

Xudong Wan, Andy Zhou, Fjord Zhang, Jerry Li, Xiaolan Gu, Evert Mos, Aernout Kisteman, Vivien Wang, Ron Schuurhuis

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.547586

KEYWORDS: Overlay metrology, Process control, Data modeling, Semiconducting wafers, Control systems, Metals, Computer simulations, Databases, Manufacturing, Phase modulation

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Proceedings Article | 16 July 2002 Paper

Advances in process overlay on 300-mm wafers

Jens Staecker, Stefanie Arendt, Karl Schumacher, Evert Mos, Richard van Haren, Maurits van der Schaar, Remi Edart, Wolfgang Demmerle, Hoite Tolsma

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473421

KEYWORDS: Semiconducting wafers, Optical alignment, Metrology, Overlay metrology, Photoresist processing, Oxides, Diffraction, Polishing, Image processing, Sensors

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Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.

Proceedings Article | 22 August 2001 Paper

Advances in process overlay

Paul Hinnen, Henry Megens, Maurits van der Schaar, Richard van Haren, Evert Mos, Sanjay Lalbahadoersing, Frank Bornebroek, David Laidler

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436734

KEYWORDS: Semiconducting wafers, Optical alignment, Copper, Overlay metrology, Metals, Metrology, Silicon, Aluminum, Chemical mechanical planarization, Polishing

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Proceedings Article | 4 December 1998 Paper

Neural network experiment demonstrating all optical data switching

Evert Mos, H. de Waardt, J. Schleipen

Proceedings Volume 3491, (1998) https://doi.org/10.1117/12.328607

KEYWORDS: Neural networks, Switching, Semiconductor lasers, Neurons, LCDs, Laser optics, Optical matrix switches, Mirrors, Telecommunications, Networks

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Showing 5 of 10 publications

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