KEYWORDS: Overlay metrology, Scanning electron microscopy, Image segmentation, Sensors, Image processing, Semiconducting wafers, Detection and tracking algorithms, Electron beams, Signal to noise ratio, Lithography
We present an overlay measurement method that is designed to use scanning electron microscope (SEM) images taken in the circuit pattern region. In the semiconductor manufacturing, the overlay is currently measured using target patterns fabricated in the scribe line region. However, there are residual errors between the measurement values in the scribe line region and the actual values in the circuit pattern region. Therefore, in-die overlay accuracy measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay accuracy measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured in the circuit pattern region. Each layer is automatically recognized from the images by utilizing a “graph cut” technique, and the placement error between the two images is determined and used to calculate the overlay accuracy. This enables us to measure the overlay accuracy without specially designed target patterns or the setting up of measurement cursors. In the numerical experiments using pseudoimages, the proposed method has linearity and sensitivity for the subpixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using real SEM images. A measurement repeatability of less than 1.35 nm (0.36 pixel) was achieved, and a reasonable wafer map of the overlay was obtained.
As device dimensions shrink, the measurement of layer-to-layer overlay is becoming increasingly important. Overlay is currently measured using target patterns fabricated within scribe lines. However, there are residual errors between the measurement values at the scribe lines and the actual values at the circuit pattern regions. Therefore, in-die overlay measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured at the circuit pattern region. Each layer is automatically recognized from the images, and the placement error between the two images is determined and used to calculate the overlay. This enables measurement without a specially designed target pattern or the setting up of measurement cursors. In the simulation experiments, the proposed method has linearity and sensitivity for the sub-pixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using a defect review SEM. For advanced memory devices, a measurement repeatability of less than 1.0 nm was achieved, and a reasonable wafer map of the overlay was obtained.
As the pattern size shrinkage, it becomes more important to control the critical size of various pattern shapes at
a semiconductor production line. Recently, in a semiconductor process with 20 nm nodes size or less the common
optical and even EB inspection tool have considerable limitation to detect critical physical defects.
From these backgrounds, we have developed the high-sensitivity fixed point inspection tool based on
Review-SEM as the product accomplishment judgment tool for below 10nm size defects on critical size devices.
We examined the basic performance of this inspection tool, optimized inspection parameters including beam
condition and image processing. Then, the defect detection performance was evaluated using various real advanced
memory device containing various critical defects. In this paper, we report these results and show the effectiveness
of this inspection tool to the advanced memory devices.
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