Simulation of negative tone development (NTD) resist has become a challenge for physical resist modeling. Traditionally, resist modeling was mainly limited to reaction-diffusion models for post exposure bake (PEB) and standard development rate models for simulating the pattern formation during the final development step. With some minor extensions, this simulation approach sufficiently predicted resist CDs and resist profile shapes that were in agreement with experimental data.3 For the latest NTD resists, this situation has changed. In contrast to positive tone development (PTD) resists, resist shrinkage is strongly impacting resist profile shapes. Furthermore, NTD resists induce strong proximity effects that require consideration of additional chemical resist properties in modeling and model calibration. In this paper we experimentally characterize and model the main properties of NTD photo-resists.
In this paper we demonstrate the feasibility of Negative Tone Development (NTD) process to pattern 22nm node contact
holes leveraging freeform source and model based assist features. We demonstrate this combined technology with
detailed simulation and wafer results. Analysis also includes further improvement achievable using a freeform source
compared to a conventional standard source while keeping the mask optimization approaches the same. Similar studies
are performed using the Positive Tone Development (PTD) process to demonstrate the benefits of the NTD process.
Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moore's Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.
Contact lithography for the 100nm generation is a difficult challenge with current layer 193nm resist processes. The SIA roadmap lists the contact hole size for 100 nm lithography as 115 nm. Even with next generation very high NA (>0.7) 193nm exposure tools, early results indicate that these contact hole sizes can not be obtained with standard processing techniques. Therefore, we have investigated the feasibility of using resist reflow to obtain small contact hole sizes.
Manufacturable process windows for the small contact dimensions of the 100nm lithography generation are well beyond the capability of current 193nm resist and exposure tool processes. Even with next generation very high NA 193nm exposure tools, simulations indicate that these contact sizes are not obtainable with standard processing techniques. Therefore, we have investigated the feasibility of using a 193nm resist reflow technique to obtain small contact hole sizes. We have chosen the thin imaging system 2000 of ARCH Chemicals for investigation. This resist provides good process latitudes and excellent etch selectivity and has a much lower Tg compared to single layer 193nm resists. This work will show the impact of resist flow on Focus-Exposure windows, proximity-uniformity, CD- uniformity over the wafer and mask error factor. Additional experimental results will highlight profiles after oxide etch as well as process windows achievable with a 6 percent attenuated phase shift mask.
Thin imaging systems have the potential for excellent lithographic performance and good etch properties. In such systems, the optical absorption of the undercoat and of the imaging layer can be adjusted through formulation and chemistry modifications. As the substrate underneath the resist undercoat changes, the optimal k for the undercoat will change. The reflectivity of the underlayer resist interface will be roughly proportional to the square of the k of the underlayer. As k gets bigger the standing wave in the resist gets stronger, but the effects of varying substrate layer thickness underneath the underlayer are suppressed. It is found that even for very reflective substrate stacks, both types of reflectivity effects are minimal with an undercoat k of about 0.20 to 0.25. The optimal underlayer k depends on how thicken an underlay er is used. Such a system gives better control of reflection and topographic effects than does a single layer plus BARC system. Experiments with different underlayers having different k's show that k can be varied chemically while retaining good etch performance.
In this work, die-to-die CD-variations across a wafer are investigated as a potential important contribution to the global gate CD-control. Measuring the non-uniformity in different experiments using CD-SEM and ELM revealed different parameters, impacting the measured non-uniformity value. It will be pointed out that the measurement itself can have a significant contribution to the measured 3(sigma) -value, especially using CD-SEM, if the level in non-uniformity is low. Further on, it will be shown that the choice of resist and developer chemistry can have a high impact on the i-W CD non-uniformity. Moreover, the potential impact of exposure and track processing will be outlined, and an optimization methodology will be presented. Finally, it will be shown that gate process integration, in particular BARC- and POLY-etching, is increasing the i-W CD non-uniformity. This is affecting the ELM-results, despite the high precision and repeatability of these measurements. This ELM-variation, as well as the overall i-W CD non- uniformity should be taken into account when using ELM or CD-SEM as a metrology tool for process window characterization.
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