The laser impacts on the proximity error are well known in many previous studies and papers. The proximity budget control is more and more important for advanced node design. The goal of this paper is to describe the laser spectral bandwidth and wavelength stability contributions to the proximity budget by considering general line/space and trench pattern design. We performed experiments and modeled the photolithography response using Panoramic Technology HyperLith simulation over a range of laser bandwidth and wavelength stability conditions to quantify the long term and short term stability contributions on wafer-to-wafer and field-to-field proximity variation. Finally, we determine the requirements for current system performance to meet patterning requirements and minimize the laser contribution on proximity error and within 4% of target CD Critical Dimension Uniformity (CDU) budget process requirement [2]. This paper also discusses how the wafer lithography drivers are enabled by ArFi light source technologies.
As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution
required and various double patterning techniques have become the main stream prior to the availability of EUV
lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch
(LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process
margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially
for topography issues induced by the 1st mask patterning with the 2nd mask exposure. In this paper, laser parameters,
topography issues with the 2nd mask exposure, and SMO effects on CD performances are described in terms of the
proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the
photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic
performance was calculated and used to illustrate the importance of well-controlled laser performance parameters.
Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to
ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Scanners, Back end of line, Lithography, 3D metrology, Finite element methods, Scatterometry, Critical dimension metrology
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput).
Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at
ASML. Authors have already published results of a thorough investigation of this promising new metrology
technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and
advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from
YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications.
Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.
Given the continually decreasing k1 factor and process latitude in advanced technology nodes, it is important to fully
understand and control the variables that impact imaging behavior in the lithography process. In this joint work between
TSMC and ASML, we use model-based simulations to characterize and predict the imaging effects of these variables
and to fine-tune the scanner settings based on such information in order to achieve optimal printing results on a perreticle
basis. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for
accurate model construction. Simulations based on the calibrated model are subsequently used to predict the wafer
impact of changes in tunable scanner parameters for all critical patterns in the product. The critical patterns can be
identified beforehand, either experimentally on wafer, mask or through model simulations. A set of optimized scanner
setting offsets, known as a "scanner tuning recipe" is generated to improve the imaging behavior for the critical patterns.
We have demonstrated the efficacy of this methodology for multiple-use cases with selected ASML scanners and TSMC
processes and will share the achieved improvements on defect reduction and yield improvements.
KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Scanners, Lithography, Back end of line, Metals, Scatterometry, Front end of line, Signal to noise ratio
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level [4].
Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have
already published results of a thorough investigation of this promising new metrology technique which showed
excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for
CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform.
This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus)
and product wafer applications.
A brand new CD metrology technique that can address the need for accuracy, precision and speed in near future
lithography is probably one of the most challenging items. CDSEMs have served this need for a long time,
however, a change of or an addition to this traditional approach is inevitable as the increase in the need for better
precision (tight CDU budget) and speed (driven by the demand for increase in sampling) continues to drive the
need for advanced nodes.
The success of CD measurement with scatterometry remains in the capability to model the resist grating, such as,
CD and shape (side wall angle), as well as the under-lying layers (thickness and material property). Things are
relatively easier for the cases with isotropic under-lying layers (that consists of single refractive or absorption
indices). However, a real challenge to such a technique becomes evident when one or more of the under-lying
layers are anisotropic.
In this technical presentation the authors would like to evaluate such CD reconstruction technology, a new
scatterometry based platform under development at ASML, which can handle bi-refringent non-patterned layers
with uniaxial anisotropy in the underlying stack. In the RCWA code for the bi-refringent case, the elegant
formalism of the enhanced transmittance matrix can still be used. In this paper, measurement methods and data
will be discussed from several complex production stacks (layers). With inclusion of the bi-refringent modeling,
the in-plane and perpendicular n and k values can be treated as floating parameters for the bi-refringent layer, so
that very robust CD-reconstruction is achieved with low reconstruction residuals. As a function of position over
the wafer, significant variations of the perpendicular n and k values are observed, with a typical radial fingerprint
on the wafer, whereas the variations in the in-plane n and k values are seen to be considerably lower.
A new metrology technique is being evaluated to address the need for accuracy, precision, speed and sophistication in metrology in near-future lithography. Attention must be paid to these stringent requirements as the current metrology capabilities may not be sufficient to support these near future needs. Sub-nanometer requirements in accuracy and precision along with the demand for increase in sampling triggers the need for such evaluation.
This is a continuation of the work published at SPIE Asia conference, 2008. In this technical presentation the authors would like to continue on reporting the newest results from this evaluation of such technology, a new scatterometry based platform under development at ASML, which has the potential to support the future needs.
Extensive data collection and tests are ongoing for both CD and overlay. Previous data showed overlay performance on production layers [1] that meet 22 nm node requirements. The new data discussed in this presentation is from further investigation on more process robust overlay targets and smaller target designs. Initial
CD evaluation data is also discussed.
Given the decrease in k1 factor for 65nm-node lithography technology and beyond, it is increasingly important to
understand and control the variables which impact scanner imaging behavior in the lithography process. In this work, we
explore using model simulations to characterize and predict imaging effects of these variables, and then based on such
information to fine-tune the scanner settings to obtain printing results optimally matched to a reference scanner. The
scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model
construction. To identify critically mismatched patterns on a production layout, we employ the fast full-chip simulation
capability provided by Brion's Tachyon servers. Tachyon simulations are also used to predict wafer impacts of changes
in tunable scanner parameters. A set of optimized scanner variable offsets, called a "scanner tuning recipe", is generated
to minimize overall imaging mismatch between two scanners. As a proof-of-concept, we have carried out scanner tuning
procedures on selected ASML scanners. The results show improvements more than 20% on CD offset RMS values for
2D line-end patterns, production layout patterns, and the mismatched patterns identified with the full-chip simulation.
Improvements on wafer-acceptance-test results and production yield on the to-be-tuned scanner are also observed.
Control of circuit CD in a photolithographic process has become increasingly important, particularly for those advanced nodes below 45nm because it influences device performances greatly. The variation of circuit CD depends on many factors, for example, CD uniformity on reticles, focus, lens aberrations, partial coherence, photoresist performance and LASER spectral bandwidth. In this paper, we focus on LASER spectral bandwidth effects to reduce circuit CD variation. High-volume products of a leading technology node are examined and a novel LASER control function: Gas Lifetime eXtenstion (GLX) is implemented to obtain stable LASER bandwidth. The LASER bandwidth variation was stabilized by changing laser F2 gas concentration through advanced control algorithm and signal process techniques. Product photo-pattern CD variation and device electrical performances will be examined to confirm the benefits of the LASER bandwidth stabilization.
Need for accuracy, precision, speed and sophistication in metrology has increased tremendously over the past few
years. Lithography performance will increasingly depend on post patterning metrology and this dependency will
be heavily accelerated by technology shrinkage. These requirements will soon become so stringent that the
current metrology capabilities may not be sufficient to support these near future needs. Accuracy and precision
requirements approaching well into sub-nanometer range while the demand for increase in sampling also
continues, triggering the need for a new technology in this area.
In this technical presentation the authors would like to evaluate such technology that has the potential to support
the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Data on first order
diffraction based overlay shows unprecedented measurement precision. The levels of precision are so low that for
evaluation special methods has been developed and tested. In this paper overlay measurement method and data
will be discussed, as well as applicability for future nodes and novel lithography techniques. CD data will be
reported in the future technical publications.
Control of Isolated and Dense line Bias (IDB) and Line End Shortening (LES) in a lithographic process has become increasingly important, particularly for the 65nm node and below. The IDB depends on many factors, for example, focus, lens aberrations, partial coherence and laser spectral bandwidth. This work studies the impact to IDB and LES from changes in laser bandwidth at two sub-micron process nodes. Careful measurements of both FWHM and E95 bandwidth parameters of the laser spectral profile were carried out using two types of spectrometers. The spectral bandwidth was adjusted over a larger range than normally experienced during wafer exposures by carefully varying the laser operating conditions to provide controlled changes in bandwidth while maintaining all other laser performance parameters within specification. Measurements of both linewidth and LES on several substrates were made and correlated with laser bandwidth to determine the sensitivity of IDB and LES to bandwidth variation. The sensitivity of different structures to E95 bandwidth variation was assessed
In general process, there is a polymer removal step by CR-SPM (Caros' acid clean) or STD clean (Standard Clean) after spacer etching. Sometimes the particles are found by KLA scan right after CR/STD clean, but not found after spacer etching. After studying the characteristics of particles, the formation of particles is due to the polarity of OD area (active area) surface changed from hydrophilic to hydrophobic and hydrophobic particles that contained in CR/STD tank are attached on OD area surface. In this report, a whole new in-situ polarity modification concept that changing hydrophobic Si surface to hydrophilic SiO surface by adding a very short O2 plasma treatment right after spacer etch is presented. The concept is evaluated in bare silicon and TEOS control wafers, and the results reveal that O2 plasma treatment can avoid particle attachment not only effectively but also efficiently. By the experiment, in-situ five seconds' O2 plasma is implanted in spacer etching recipe and two products are split to test. The WAT (Wafer Acceptance Test) and yield of split are comparable with standard condition.
The silicon nitride spacer technology is widely used in split gate non-volatile memory device sand flash EPROM. A tiny spacer structure is formed on tunnel oxide layer adjacent to the sidewall of floating gate electrode to prevent write disturbance that caused by reverse tunneling. But the processing is very critical for such flash EPROM devices since the dimension the SN spacer are so small. It was influenced not only by SN spacer dry etching but also later photo-resistance strip process of implantation for threshold voltage adjustment. A new method of forming tiny SN spacer by using anisotropic dry etching and isotropic wet etching was presented in this paper.
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